AGATA WEEK Uppsala 7-11 July 2008

Slides:



Advertisements
Similar presentations
GCT Software Jim Brooke GCT ESR, 7 th November 2006.
Advertisements

Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2 Mother Board Design Status Exogam Collaboration Abderrahman BOUJRAD GANIL France.
Peter Chochula, January 31, 2006  Motivation for this meeting: Get together experts from different fields See what do we know See what is missing See.
Coupling an array of Neutron detectors with AGATA The phases of AGATA The AGATA GTS and data acquisition.
MICE CM15 June 2006Jean-Sébastien GraulichSlide 1 DAQ for BTF o BTF Overview o Hardware Overview o DAQ Software Description o What’s next o Summary Jean-Sebastien.
Status of LAV FEE electronics G. Corradi, C. Paglia, D. Tagnani & M. Raggi, T. Spadaro, P. Valente.
TRD DAQ (U) Software Status TIM CERN May.09 Chanhoon Chung, Mark Millinger, Andreas Sabellek IEKP - Universität Karlsruhe (TH)
VC MICO Report July 07Jean-Sébastien GraulichSlide 1 Main news  DAQ test bench running in Geneva 2 LDCs connected to 2 different PCs, 1 GDCs DAQ trigger.
9th October 2008AIDA FEE progress report P.J.Coleman-Smith 1 AIDA Frontend Electronics progress report. Mezzanine to FEE64 connection. Mezzanine Layout.
Time stamping with CAEN V1290N Bled, 26 th – 28 th March 2008 Dušan Ponikvar, Dejan Paradiž Faculty of Mathematics and Physics Ljubljana, Slovenia.
MICE CM18 June 07Jean-Sébastien GraulichSlide 1 Detector DAQ Status o Since CM17 o Detector DAQ software o Front End Electronics o Schedule Milestones.
Summary DCS Workshop - L.Jirdén1 Summary of DCS Workshop 28/29 May 01 u Aim of workshop u Program u Summary of presentations u Conclusion.
AGATA Pre-processing team report AGATA Week, July 2008.
Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Integration of ancillaries with DAQ Goal Context Specifications, modes Design Schedule &
Group Electronique Csnsm AGATA SLOW CONTROL MEETING 19th fev AGATA PROJECT PREPROCESSING MEZZANINE SLOW CONTROL GUI FOR THE SEGMENT AND THE CORE.
Coupling Neutron Detector array (NEDA) with AGATA The AGATA Front-End processing Electronics & DAQ The AGATA Trigger and Synchronization (GTS) Coupling.
Straw Electronics status and preparation for the technical run NA62 workshop Siena.
DAQ MICO Report Online Monitoring: –Status All histograms are now implemented Still not fully online –Only monitoring from data file (slightly offline,
DAQ & ECS for TPC commissioning A few statements about what has been done and what is still in front of us F.Carena.
1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 3 Report Jack Hickish.
S. Brambilla, “Recent DAQ integration test at L.N.L May 2008” 7 th AGATA Week, Uppsala, 8-11 July th AGATA Week Uppsala, 8-11 July 2008 Recent.
Status of Global Trigger Global Muon Trigger Sept 2001 Vienna CMS-group presented by A.Taurok.
FADC progress in Vienna Reported by H.Ishino for Vienna FADC group M.Pernicka and H.Steininger.
Controls EN-ICE Finite States Machines An introduction Marco Boccioli FSM model(s) of detector control 26 th April 2011.
Summary talk of Session 6 - Electronics and Interfacing to AD DAQ - Mechanics for the Demonstrator for the AD ancillary detector integration team: for.
DABCDABC J. Adamczewski-Musch, H.G. Essel, S. Linev Software development for CBM DAQ J. Adamczewski-Musch, H.G. Essel, S.
Bernardo Mota (CERN PH/ED) 17/05/04ALICE TPC Meeting Progress on the RCU Prototyping Bernardo Mota CERN PH/ED Overview Architecture Trigger and Clock Distribution.
FED RAL: Greg Iles5 March The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality.
LKR Working group Introduction R. Fantechi October 27 th, 2009.
John Coughlan Tracker Week October FED Status Production Status Acceptance Testing.
DAQ Status for cosmic-ray test in RAL Hideyuki Sakamoto MICE Phone meeting 12 th July 2007 Contents Status Setup for cosmic-ray test bench Schedule.
1 October 2003Paul Dauncey1 Mechanics components will be complete by end of year To assemble ECAL, they need the VFE boards VFE boards require VFE chips.
Beam diagnostics developments at LAPP: Digital part CTF3 Collaboration Meeting Louis Bellier, Richard Hermel, Yannis Karyotakis, Jean Tassan,
CM19 Vassil Verguilov DAQ Status  Progress  DAQ  Next steps  Summary.
Bottom half – ch 0-5 placed & routed FE PS PROC FIFO TRIG OSC RX/SHAP ADC DAC VME.
Configuration database status report Eric van Herwijnen September 29 th 2004 work done by: Lana Abadie Felix Schmidt-Eisenlohr.
5th March 0718th DCS Workshop1 News on ISEG & WIENER Lionel Wallet, CERN High Voltage, Low Voltage & VME Crate control.
FEE Electronics progress Mezzanine layout progress FEE64 progress FEE64 initial testing Test mezzanine. A few of the remaining tasks 2nd October 2009.
October Test Beam DAQ. Framework sketch Only DAQs subprograms works during spills Each subprogram produces an output each spill Each dependant subprogram.
R. Fantechi. Shutdown work Refurbishment of transceiver power supplies Work almost finished in Orsay Small crisis 20 days ago due to late delivery of.
HPS TDAQ Review Sergey Boyarinov, Ben Raydo JLAB June 18, 2014.
Pulsar Hardware Status Burkard Reisert (FNAL) March, 14 th 2003.
CBM-TOF-FEE Jochen Frühauf, GSI Picosecond-TDC-Meeting.
Mai 31th 2011 Christophe Beigbeder PID meeting1 ETD meeting Test setup : Activities in Bari, Univ of Maryland and at Orsay Test setup : Activities in Bari,
DAQ / Trigger Card for HCAL SLHC Readout E. Hazen - Boston University
Gu Minhao, DAQ group Experimental Center of IHEP February 2011
Novosibirsk, September, 2017
CLAS12 DAQ & Trigger Status
LKr status R. Fantechi.
FTK infrastructure in USA15 Status and plans for 2015 A
Front-end and VME / VXI readout electronics for ASICs
AHCAL Beam Interface (BIF)
Commissioning the SIS3316 Digitizer
Pipeline Leak Detection Device
APV Readout Controllers DAQ
ALICE Trigger Upgrade CTP and LTU PRR
TDCB status Jacopo Pinzino, Stefano Venditti
EMU Alignment DAQ Endcap Alignment Muon Alignment EDR Feb. 28, 2002
LLRF Controls Outline Requirements External Interfaces Schedule Design
Hall A Compton Electron detector overview
Slot number is not critical. Traditionally, Slot 2: ADC,
Retail Market Messaging Support Issues
Status of the Design & Development of the AGAVA interface module.
University of California Los Angeles
M. Krivda for the ALICE trigger project, University of Birmingham, UK
Testbeam status report
ZDD status BESIII Collaboration Meeting, September 2012
Command and Data Handling
3 Week A: May 1 – 19 3 Week B: May 22 – June 9
The QUIET ADC Implementation
Presentation transcript:

AGATA WEEK Uppsala 7-11 July 2008 AGAVA INTERACE Barbara Dulny 1/17/2019 AGATA WEEK Uppsala 7-11 July 2008

AGATA WEEK Uppsala 7-11 July 2008 Overview Tests in VXI system at Ganil Tests in CBLT mode at Legnaro Test of new release of AGAVA with the new release of GTS mezzanine card Plans 1/17/2019 AGATA WEEK Uppsala 7-11 July 2008

Tests in VXI system at Ganil Tests of AGAVA in VXI environment done in October 2007 with Frederic Saillant and Co. Tests were not finished because of time limitation and have to be continued It was agreed to continue the tests with the new version of AGAVA The new AGAVA is ready for the tests since May 2008 1/17/2019 AGATA WEEK Uppsala 7-11 July 2008

Tests in CBLT mode at Legnaro The test of CBLT mode was done in Legnaro on 5- 9 May 2008 with Sergio Brambilla Test was done using Struck PCI/cPCI to VME interface, AGAVA board release 1 and 2, CAEN V775 32 channel TDC, CAEN V785 32 channel ADC CAEN V538A 8channel NIM-ECL/ECL-NIM Translator AGAVA was the first, TDC intermediate, ADC last in the chain External trigger (~20kHz pulser) was used for AGAVA input KMAX software was used on the Struck for control and data collection Test was running whole night (>8 hours) with total acqusition rate ~10 kHz 1/17/2019 AGATA WEEK Uppsala 7-11 July 2008

Tests of new release of AGAVA The AGAVA rel. 2 was tested in the same configuration as rel.1 in the CBLT mode and standard VME access mode successfuly As the GTS release 1 (based on Virtex 2Pro) will be not produced anymore it was necessary to test AGAVA board with the new GTS release 2 (based on Virtex 4) The tests of AGAVA release 1 and 2 with new GTS (release2) have been done in CBLT and standard mode successfully The test of the Ethernet connection to the GTS via AGAVA release 2 was not successful because there were still missing components on the AGAVA release 2 (promissed from GTS team) The Ethernet connection test should be tested. 1/17/2019 AGATA WEEK Uppsala 7-11 July 2008

AGATA WEEK Uppsala 7-11 July 2008 Next Continue tests in the VXI environment at Ganil Test of Ethernet connection to the GTS via AGAVA board release 2. 1/17/2019 AGATA WEEK Uppsala 7-11 July 2008