T.H.A.D.D. GROUP TOM DUAN HELEN YU ANDY LEE DANNY HUANG DAWEY HUANG

Slides:



Advertisements
Similar presentations
Final Project : Pipelined Microprocessor Joseph Kim.
Advertisements

Instruction-Level Parallelism (ILP)
MIPS Pipelined Datapath
Lab Assignment 2: MIPS single-cycle implementation
Review: MIPS Pipeline Data and Control Paths
ENEE350 Ankur Srivastava University of Maryland, College Park Based on Slides from Mary Jane Irwin ( )
Sunshine Slam Khian Hao Lim Haywood Ho Soe Myint Leo Ting Ka Hou Chan.
1 Stalling  The easiest solution is to stall the pipeline  We could delay the AND instruction by introducing a one-cycle delay into the pipeline, sometimes.
Lec 8: Pipelining Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University.
Computer Architecture - A Pipelined Datapath A Pipelined Datapath  Resisters are used to save data between stages. 1/14.
Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____.
Ceng 450 Project. Pinout of Processor Interrupt is optional Processor in_port[7:0] out_port[7:0] clock rst interrupt.
Pipeline Data Hazards: Detection and Circumvention Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005, and from slides kindly.
Lecture 8: Processors, Introduction EEN 312: Processors: Hardware, Software, and Interfacing Department of Electrical and Computer Engineering Spring 2014,
Pipelined Datapath and Control
CPE432 Chapter 4B.1Dr. W. Abu-Sufah, UJ Chapter 4B: The Processor, Part B-2 Read Section 4.7 Adapted from Slides by Prof. Mary Jane Irwin, Penn State University.
EECE 476: Computer Architecture Slide Set #5: Implementing Pipelining Tor Aamodt Slide background: Die photo of the MIPS R2000 (first commercial MIPS microprocessor)
CMPE 421 Parallel Computer Architecture Part 2: Hardware Solution: Forwarding.
TEAM FRONT END ECEN 4243 Digital Computer Design.
CDA 4253 FPGA System Design RTL Design Methodology 1 Hao Zheng Comp Sci & Eng USF.
CSIE30300 Computer Architecture Unit 05: Overcoming Data Hazards Hsin-Chou Chi [Adapted from material by and
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB ECE232: Hardware Organization and Design Part 13: Branch prediction (Chapter 4/6)
PROCESSOR PIPELINING YASSER MOHAMMAD. SINGLE DATAPATH DESIGN.
CPE432 Chapter 4B.1Dr. W. Abu-Sufah, UJ Chapter 4B: The Processor, Part B-1 Read Sections 4.7 Adapted from Slides by Prof. Mary Jane Irwin, Penn State.
Pipelining: Implementation CPSC 252 Computer Organization Ellen Walker, Hiram College.
CSE 340 Computer Architecture Spring 2016 Overcoming Data Hazards.
Interstage Buffers 1 Computer Organization II © McQuain Pipeline Timing Issues Consider executing: add $t2, $t1, $t0 sub $t3, $t1, $t0 or.
STUDY OF PIC MICROCONTROLLERS.. Design Flow C CODE Hex File Assembly Code Compiler Assembler Chip Programming.
Pipeline Timing Issues
Computer Organization
Stalling delays the entire pipeline
Variable Word Width Computation for Low Power
Note how everything goes left to right, except …
CDA 3101 Spring 2016 Introduction to Computer Organization
Single Clock Datapath With Control
Appendix C Pipeline implementation
ECS 154B Computer Architecture II Spring 2009
ECS 154B Computer Architecture II Spring 2009
ECE232: Hardware Organization and Design
Forwarding Now, we’ll introduce some problems that data hazards can cause for our pipelined processor, and show how to handle them with forwarding.
Chapter 4 The Processor Part 3
Review: MIPS Pipeline Data and Control Paths
Morgan Kaufmann Publishers The Processor
Morgan Kaufmann Publishers The Processor
SOLUTIONS CHAPTER 4.
Pipelining review.
Team A.W.E.S.O.M.-O 4000 February 20, 2007.
Current Design.
Pipelining in more detail
Data Hazards Data Hazard
Pipeline control unit (highly abstracted)
The Processor Lecture 3.6: Control Hazards
Control unit extension for data hazards
Guest Lecturer TA: Shreyas Chand
The Processor Lecture 3.5: Data Hazards
Instruction Execution Cycle
Overview What are pipeline hazards? Types of hazards
Pipeline control unit (highly abstracted)
Pipelining: Basic Concepts
pipelining: data hazards Prof. Eric Rotenberg
Pipeline Control unit (highly abstracted)
Pipelining (II).
Control unit extension for data hazards
Morgan Kaufmann Publishers The Processor
Introduction to Computer Organization and Architecture
Control unit extension for data hazards
Computer Architecture Assembly Language
MIPS Pipelined Datapath
©2003 Craig Zilles (derived from slides by Howard Huang)
ELEC / Computer Architecture and Design Spring 2015 Pipeline Control and Performance (Chapter 6) Vishwani D. Agrawal James J. Danaher.
Presentation transcript:

T.H.A.D.D. GROUP TOM DUAN HELEN YU ANDY LEE DANNY HUANG DAWEY HUANG DSP Enabled Processor Design T.H.A.D.D. GROUP TOM DUAN HELEN YU ANDY LEE DANNY HUANG DAWEY HUANG

Agenda Datapath Design Memory Subsystem Power Optimization Performance

5-Stage Pipeline IF/ID PIPELINE REG ID/EX PIPELINE REG EX/MEM PIPELINE REG MEM/WB PIPELINE REG INSTRUCTION CACHE REGISTER FILE DATA CACHE MAC STAGE 1 MAC STAGE 2 BRANCH LOGIC ALU JUMP LOGIC

Multiply and Accumulate 2-stage pipeline multiplier No stalling when LW followed by MAC ID/EX PIPELINE REG EX/MEM PIPELINE REG MEM/WB PIPELINE REG REGISTER FILE MULTIPIER 1 MULTIPIER 2

Critical Path (WB stage) MEM/WB PIPELINE REG 16 MAC STAGE 2 FROM DATA MEMORY 16 32 32 MUX 32 32 32 TO REGISTER FILE

Memory Subsystem 2x clock rate of processor 3 controllers sdram instruction block data block asynchronous component interface (arbitrator)

Clock Divider CLK ICLK Counter CLK2X

Memory Subsystem Diagram INSTRUCTION CACHE BLOCK DATA CACHE BLOCK BUFFER CACHE CONTROL CONTROL MAIN CACHE VICTIM CACHE miss data miss data address address ARBITRATOR ready ready address SDRAM BLOCK SDRAM (GIVEN) CONTROLLER ready

Cache Organization

Instruction Cache/Controller ADDRESS Cache Blocks Controller FSM 5 BLOCKS EACH 4 WORDS DATA ADDRESS HIT CLK IDLE WORD READ WRITE DISABLE CHECK SDRAM READY MISS SDRAM DATA MISS SDRAM ADDRESS DOUT

Data Cache

Data Cache <-> Victim Cache

Power Reduction Methods Limiting VHDL sensitivity list Balance input arrival Enable/Disable components Eliminate unnecessary control signals & data buses Minimize execution time to lower supply voltage

Power Consumption of Components Supply voltage = 2.5Volts

Component Optimization Results (1) Supply voltage = 2.5Volts

Component Optimization Results (2) Supply voltage = 2.5Volts

Supply Voltage Reduction Results

Supply Voltage Comparison

Design Challenges what we learned: power optimization concepts what surprised us: component interface timing what challenged us: reducing cache miss

Conclusion A Very Rewarding Project Excellent Performance Can Sleep Again!