Day 2: September 10, 2010 Transistor Introduction ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: September 10, 2010 Transistor Introduction Penn ESE370 Fall2010 -- DeHon
Today MOSFET Capacitive and resistive loads Simplified models Zero-th order model Good enough for ??? First order model There are always Rs and Cs Penn ESE370 Fall2010 -- DeHon
MOSFET Metal Oxide Semiconductor Field Effect Transistor New device Primary active component for the term Three terminal device Voltage at gate controls conduction between two other terminals (source, drain) Penn ESE370 Fall2010 -- DeHon
MOSFET I vs. Vgs, Vds Penn ESE370 Fall2010 -- DeHon
MOSFET I vs. Vgs, Vds Will dig into understanding during term Today simple ways to reason about gross behavior Static/DC Penn ESE370 Fall2010 -- DeHon
Preclass What voltage do the cases converge to? Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
Conclude? DC/Steady-State Ignore the capacitors Penn ESE370 Fall2010 -- DeHon
Quasistatic Static – inputs (and circuit) unchanging, how does it settle? Dynamic – what happens when things change Quasi-Static – inputs transition, circuit responds, and settles Dynamic transition to roughly static states Penn ESE370 Fall2010 -- DeHon
Quasistatic Relevance? How relevant to a combinational digital circuit? How relevant to a clocked digital circuit? Penn ESE370 Fall2010 -- DeHon
Zero-th Order MOSFET Ideal Switch Vgs > Vth conducts Vgs < Vth does not conduct Vth – threshold voltage Penn ESE370 Fall2010 -- DeHon
Zero-th Order MOSFET Penn ESE370 Fall2010 -- DeHon
N-Type, P-Type N – negative carriers Switch turned on positive Vgs electrons Switch turned on positive Vgs P – positive carriers holes Switch turned on negative Vgs Vth<0 Vgs<Vth to to conduct Penn ESE370 Fall2010 -- DeHon
Why useful? Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=0 > Vth Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=0 > Vth Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=0 > Vth V2=Gnd Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=0 > Vth V2=Gnd Vgs=0 < Vth Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=-Vdd < Vth Vgs=0 > Vth V2=Gnd Vgs=0 < Vth Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=Vdd>Vth Vgs=-Vdd < Vth Vgs=0 > Vth Vout=Vdd V2=Gnd Vgs=0 < Vth Vgs=Vdd > Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=0<Vth Penn ESE370 Fall2010 -- DeHon
What happens when Vin=0<Vth V2=Vdd Vout=0 Penn ESE370 Fall2010 -- DeHon
What function? Buffer Vin=Vdd Vout=Vdd Vin=0 Vout=0 Penn ESE370 Fall2010 -- DeHon
Why Useful? Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Penn ESE370 Fall2010 -- DeHon
Why adequate? Static analysis – can ignore capacitors Capacitive loads – resistances don’t matter Feed forward for gates – don’t generally have loops can work forward from known values Logic drive rail-to-rail Don’t have to reason about intermediate voltage levels Penn ESE370 Fall2010 -- DeHon
What not tell us? Delay Dynamics Behavior if not Capacitively loaded Loops Penn ESE370 Fall2010 -- DeHon
First Order Model Switch Loads input capacitively Has finite drive strength Penn ESE370 Fall2010 -- DeHon
First Order Model Penn ESE370 Fall2010 -- DeHon
First Order Model Penn ESE370 Fall2010 -- DeHon
Refine to First Order Penn ESE370 Fall2010 -- DeHon
Zero-th Order Tells us how switches set (Vin=0) V2=Vdd Vout=0 Penn ESE370 Fall2010 -- DeHon
Zero-th Order Tells us how switches set (Vin=0) V2=Vdd Vout=0 Penn ESE370 Fall2010 -- DeHon
Zero-th Order Tells us how switches set (Vin=0) Leaves an RC Circuit we can analyze Penn ESE370 Fall2010 -- DeHon
Zero-th Order Tells us how switches set (Vin=0) Look at middle stage Penn ESE370 Fall2010 -- DeHon
What more this tell us? Delay Quastistatic behavior Voltage settling with resistive loads At least some basis for reasoning Penn ESE370 Fall2010 -- DeHon
What is this leaving out? Penn ESE370 Fall2010 -- DeHon
What is this leaving out? Penn ESE370 Fall2010 -- DeHon
What leaving out? What happens at intermediate voltages Not rail-to-rail Details of dynamics, including… Input not transition as step Intermediate drive strengths change with Vgs As output charges Vds changes, changing drive strenght Isn’t really 0 current below threshold Penn ESE370 Fall2010 -- DeHon
Engineering Control Vth – process engineer Drive strength – circuit engineer control with sizing Supply voltages – range set by process, detail use by circuit design Penn ESE370 Fall2010 -- DeHon
Engineering Control: Threshold Penn ESE370 Fall2010 -- DeHon
Engineering Control: Drive Strength Penn ESE370 Fall2010 -- DeHon
Wire Capacitance Penn ESE370 Fall2010 -- DeHon
Wire Capacitance Penn ESE370 Fall2010 -- DeHon
Wire Resistance Penn ESE370 Fall2010 -- DeHon
Wire Resistance Penn ESE370 Fall2010 -- DeHon
Wire Resistance Sanity check Wire twice as long = resistors in series Wire twice as wide = resistors in parallel Penn ESE370 Fall2010 -- DeHon
There are always Rs and Cs Modeling vs. discrete components Dominant effects Rbig + Rsmall ≈ Rbig Cbig || Csmall ≈ Csmall Penn ESE370 Fall2010 -- DeHon
Admin TA: Andrew Townley Lecture Monday: building gates Email: atownley seas Office Hours: Lecture Monday: building gates Reading Lab on Wednesday Penn ESE370 Fall2010 -- DeHon
MOSFET Penn ESE370 Fall2010 -- DeHon
Big Ideas MOSFET Transistor as switch Purpose-driven simplified modeling Aid reasoning Sanity check Simplify design New perspective on Rs and Cs Penn ESE370 Fall2010 -- DeHon