Bit Multiplexed Real Time Network – A Novel Approach to Real-Time Networking Introduction Design Implementation Future Work Paul Richardson Mukul Gadde University of Michigan-Dearborn 1/17/2019 NDIA-IVS 2003

Real-Time Networks A network in which messages have explicit or implicit time constraints Correct operations defined in terms of both reliable and timely delivery of data Some Data is Critical Data – Untimely Delivery can Result in Damage or Injury 1/17/2019 NDIA-IVS 2003

Temporal Components of a Message’s Transmission (1) Local Host Delay from Buffering (2) Transmission Time – Number of Bits  Bit Period (3) Signal Propagation Delay – Determined by Geographic Distance (4) Network Delay – From Contention Between Nodes NIC Application tsend treceive tnet tlocal tTX tprop 1/17/2019 NDIA-IVS 2003

Guaranteed Message Time Constraints - Classical Approach For Each Message  Determine Worst Case Response Time (WCRT) If WCRT < Deadline  Message will be on Time, else it can be Late WCRT = tprop + tTX + tlocal + tnet Propagation Delay: constant, often negligible Transmission Time: constant per frame size - can easily be determined typically tTX << Deadline Local Delay: Depends Only on Local Traffic – Determined Independently Network Delay: Depends on All Network Traffic – Most Unpredictable of all Temporal Components 1/17/2019 NDIA-IVS 2003

WCRT = tprop + tTX + tlocal Objectives of Bit Multiplexing Eliminate Network Delay Component Removes Network Wide Timing Dependencies Eliminates Trade-Off Between Frame Sizes Reduce Variance in WCRT – More Efficient Simple Design – Easy to Implement Using FPGAs WCRT = tprop + tTX + tlocal tnet eliminated tlocal will increase by a factor of n for n nodes 1/17/2019 NDIA-IVS 2003

What is Bit Multiplexing? The Network is Shared on a BIT boundary – not on the FRAME boundary Each node is assigned a time slot to transmit a bit Frames are rebuilt from recovered bits idle bit patterns are sent during idle time to maintain synchronization NIC Application tnet tsend treceive tlocal tprop tbit 1/17/2019 NDIA-IVS 2003

Result - Each Node Perceives its Own Dedicated Physical Channel Ideally - Aggregate Data Rate Remains the Same In Most Cases – WCRT will be Lower Application Application Application NIC NIC NIC 1/17/2019 NDIA-IVS 2003

Primary Modules of a Node Synchronization Module Transmitter Module (Tx) Receiver Module (Rx) Synch Counter Transmitter Receiver transmit buffer receive buffer transmission medium 1/17/2019 NDIA-IVS 2003

Synch Module – Manchester Codes Counter Transmitter Receiver reset 30 counter enable edge detector 32clk slot counter RX enable, TX disable or TX enable, RX disable 0 0 1 A B C Module Initialization power up register configuration Counter determines current “slot” enables signals for Tx and Rx 1/17/2019 NDIA-IVS 2003

Transmit Module Node C slot counter 0 0 1 16 counter enable TX C A B C Synch Counter Transmitter Receiver 0 0 1 A B C 30 counter edge detector 32clk slot counter enable TX C transmit frame buffer 1 16 counter 1/17/2019 NDIA-IVS 2003

Receive Module Node A select slot counter 0 0 1 8 counter enable RX B Synch Counter Transmitter Receiver 0 0 1 A B C 30 counter edge detector 32clk slot counter receive frame buffers 1 slot B slot C select enable RX B 8 counter destination address encoded in frame 1/17/2019 NDIA-IVS 2003

Implementation – Proof of Principal Using VHDL and 3 Xilinx XC4010E/XL Boards 7000 Gates Used for Each Node (10,000 Maximum) 4 Input/Output Channels Used (160 Maximum) Transmit Data: Static Characters from RAM Buffer Receive Data: Displayed on 7-Segment Displays Aggregate 600KHz Signal Rate  300Kbps Data Rate Individual Node Rate = 100Kbps NODE A TX RX NODE B NODE C 1/17/2019 NDIA-IVS 2003

Next Phase: interconnect computers via PCI Follow on work Next Phase: interconnect computers via PCI receive data – save to RAM & display to CRT send data files, images, etc Increase data rate (10-100Mbps) Add Fault Tolerance – Sustain Network Faults Increase Scalability – Add/Remove Nodes 1/17/2019 NDIA-IVS 2003

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