The Map Method Truth table of fn is unique but fn can be in many different algebraic forms Simplification by using boolean algebra is often difficult because.

Slides:



Advertisements
Similar presentations
Digital Logic Design Gate-Level Minimization
Advertisements

Chapter3: Gate-Level Minimization Part 2
CENG 241 Digital Design 1 Lecture 4
Gate-Level Minimization
Boolean Algebra and Reduction Techniques
Chapter 3 Simplification of Switching Functions. Karnaugh Maps (K-Map) A K-Map is a graphical representation of a logic function’s truth table.
Gate-level Minimization
Boolean Algebra and Combinational Logic
Gate-Level Minimization. Digital Circuits The Map Method The complexity of the digital logic gates the complexity of the algebraic expression.
Relationship Between Basic Operation of Boolean and Basic Logic Gate The basic construction of a logical circuit is gates Gate is an electronic circuit.
Chapter 4 Logic Gates and Boolean Algebra. Introduction Logic gates are the actual physical implementations of the logical operators. These gates form.
Computer Engineering (Logic Circuits) (Karnaugh Map)
بهينه سازي با نقشة کارنو Karnaugh Map. 2  Method of graphically representing the truth table that helps visualize adjacencies 2-variable K-map 3-variable.
Chapter 2: Combinatorial Logic Circuits Illustration Pg. 32 Logic Circuit Diagrams - Circuit Optimization -2,3,4 level maps 48 elements Optimized to 25.
Chapter 10.1 and 10.2: Boolean Algebra Based on Slides from Discrete Mathematical Structures: Theory and Applications.
Logic Design CS221 1 st Term K-Map Cairo University Faculty of Computers and Information.
BOOLEAN ALGEBRA Saras M. Srivastava PGT (Computer Science)
1 Simplification of Boolean Functions:  An implementation of a Boolean Function requires the use of logic gates.  A smaller number of gates, with each.
1 Chapter 5 Karnaugh Maps Mei Yang ECG Logic Design 1.
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC. K-Map (1)  Karnaugh Mapping is used to minimize the number of logic gates that are required in a digital circuit.
F = ∑m(1,4,5,6,7) F = A’B’C+ (AB’C’+AB’C) + (ABC’+ABC) Use X’ + X = 1.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. Circuit Optimization Logic and Computer Design Fundamentals.
ECE 2110: Introduction to Digital Systems PoS minimization Don’t care conditions.
Circuit Minimization. It is often uneconomical to realize a logic directly from the first logic expression that pops into your head. Canonical sum and.
PRASAD A. PAWASKAR SPN. NO DETE 2 SEMESTER lec1-11.
Gate-Level Minimization
Chapter 2 Two- Level Combinational Logic. Chapter Overview Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR Gate Logic Laws and Theorems.
A.Abhari CPS2131 Chapter 3: Gate-Level Minimization Topics in this Chapter: The Map Method Two-Variable Map Three- Variable Map Four/Five variable Map.
CS 1110 Digital Logic Design
Logic Functions: XOR, XNOR
Simplification of switching functions Simplify – why? –Switching functions map to switching circuits –Simpler function  simpler circuit –Reduce hardware.
February 2, 2004CS 2311 Karnaugh maps Last time we saw applications of Boolean logic to circuit design. – The basic Boolean operations are AND, OR and.
Gate-Level Minimization Gate-Level Minimization. Outline 3.1 Introduction 3.2 The map method 3.3 Four-variable map 3.4 Five-variable map 3.5 Product of.
Karnaugh Maps (K-Maps)
CS231 Boolean Algebra1 Summary so far So far: – A bunch of Boolean algebra trickery for simplifying expressions and circuits – The algebra guarantees us.
CS151 Introduction to Digital Design Chapter Map Simplification.
Karnaugh Maps (K maps). What are Karnaugh 1 maps?  Karnaugh maps provide an alternative way of simplifying logic circuits.  Instead of using Boolean.
DKT 122/3 - DIGITAL SYSTEM I Chapter 4A:Boolean Algebra and Logic Simplification) Mohd ridzuan mohd nor
Karnaugh Maps (K-Maps)
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC
THE K-MAP.
Karnaugh Map (K-Map) By Dr. M. Khamis Mrs. Dua’a Al Sinari.
Karnaugh Maps (K maps).
Chapter 4 OPTIMIZED IMPLEMENTATION OF LOGIC FUNCTIONS.
ECE DIGITAL LOGIC LECTURE 8: BOOLEAN FUNCTIONS Assistant Prof. Fareena Saqib Florida Institute of Technology Spring 2016, 02/11/2016.
BOOLEAN ALGEBRA LOGIC GATES. Introduction British mathematician George Boole( ) was successful in finding the link between logic and mathematics.
School of Computer and Communication Engineering, UniMAP DKT 122/3 - DIGITAL SYSTEM I Chapter 4A:Boolean Algebra and Logic Simplification) Mohd ridzuan.
Lecture 07 Digital logic By Amr Al-Awamry. 4 variables K-Map.
Mu.com.lec 9. Overview Gates, latches, memories and other logic components are used to design computer systems and their subsystems Good understanding.
CHAPTER 3 Simplification of Boolean Functions
Gate-Level Minimization
ECE 2110: Introduction to Digital Systems
ECE 3110: Introduction to Digital Systems
Boolean Algebra and Combinational Logic
Karnaugh Map Method.
ECE 331 – Digital System Design
Karnaugh Maps (K-Maps)
Lecture 4 Sums of Product Circuits Simplification
BASIC & COMBINATIONAL LOGIC CIRCUIT
Digital Logic & Design Dr. Waseem Ikram Lecture 13.
SYEN 3330 Digital Systems Chapter 2 – Part 4 SYEN 3330 Digital Systems.
Combinatorial Logic Circuit
Digital Logic Design I Gate-Level Minimization
Karnaugh Mapping Digital Electronics
MINTERMS and MAXTERMS Week 3
Gate Level Minimization
Karnaugh Maps (K maps).
Circuit Simplification and
Presentation transcript:

The Map Method Truth table of fn is unique but fn can be in many different algebraic forms Simplification by using boolean algebra is often difficult because we don’t know how to proceed Map method or Karnaugh map (K_Map) is simple and straightforward method that produces minimum number of terms.

Two-Variable Map A fn variable have 2n minterms (cells)

Three- Variable Map Adjacent cells represent minterms that differs by only one variable. Therefore, adjacent cells are identical except for one variable that appears complemented in one cell and uncomplemented in the adjacent cell. Example : F(x,y,x) = ∑ (2,3,4,5)

Another example : F(x,y,z) = ∑(3,4,6,7)

Four variable Map

Multilevel NAND circuits To convert multilevel AND-OR to all NAND: Convert all ANDs with AND-invert Convert all ORs with invert-OR Check the bubbles in diagrams if any of them is not compensated by another small circle along the same line insert an inverter(One input NAND) or complement the input literal

Implementing NOR circuits To convert multilevel AND-OR to all NOR: Convert all ORs with invert-OR Convert all ANDs with invert-AND Check the bubbles in diagrams if any of them is not compensated by another small circle along the same line insert an inverter(One input NOR) or complement the input literal