13 Digital Logic Circuits

Figure 13.9 Binary and Gray code patterns for linear position encoders Decimal 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Gray code 1000 1001 1011 1010 1110 1111 1101 1100 0100 0101 0111 0110 0010 0011 0001 0000 Decimal 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1

Figure 13.10 Binary and Gray code patterns for angular position encoders 11111 Binary sequence Gray code 00000 01111 10000 01000 11000

Figure 13.14 Complements and the NOT gate X NOT gate 1 Truth table for NOT gate NOT

Figure 13.17 De Morgan’s laws X Y Z + . OR AND = NOT ( )

Figure 13.18 Sum-of-products and product-of-sum logic functions W A B C D Product of sums expression . ( + ) OR AND X Y Z Sum of products ) + (

Figure 13.21 Equivalence of NAND and NOR gates with AND and OR gates ( A + B ) = . NAND . ( A B ) = A + B NOR B B A . A B A A + B AND NOT . ( A B ) OR NOT ( A + B ) B B A B A B ( A . B ) A B A B ( A + B ) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NAND gate NOR gate

Figure 13.27 XOR gate Z = X Y X Z XOR 1 Truth table

Figure 13.28 Realization of an XOR gate Y Z NAND OR AND

Figure 13.30 Truth table and karnaugh map representations of a logic function X Y 1 Z Desired Function Truth table X Y XY Karnaugh map

Figure 13.31 Karnaugh map for a four-variable expression Y 1 Z Desired Function Truth table for four-variable expression . W

Figure 13.55 4-to-1 MUX 4-to-1 MUX Enable Data inputs E D F I Output 1 Data select Data inputs E F 4-to-1 MUX block diagram of 4-to-1 MUX D I 1 2 3 Truth table of 4-to-1 MUX

Figure 13.58 Read-only memory ROM i = output word b 1 2 3 Enable E Address lines I ROM content (4-bit words) address W 4