Finite State Machines (FSMs) Notes: Review for Test #2 – Monday Today: First Hour: Moore & Mealy Machines Section 8.4 of Katz’s Textbook In-class Activity #1 Second Hour: Reverse Engineering FSMs In-class Activity #2

Recap: Vending Machine Delivers package of gum after 15 cents is deposited Single coin slot for dimes, nickels No change given Present Inputs Next Output Reset State D N State Open 0¢ 0¢ 0¢ D 1 5¢ N 1 10¢ 1 1 X X 5¢ 5¢ 5¢ 1 10¢ D N 1 15¢ 1 1 X X 10¢ 10¢ 10¢ 1 15¢ 1 15¢ N, D 1 1 X X 15¢ 15¢ X X 15¢ 1 [open]

Positive Edge Triggered Synchronous System Recap: Timing Positive Edge Triggered Synchronous System On rising edge: inputs sampled, outputs & next state computed After propagation delay: outputs and next state are stable Immediate Outputs effective immediately Delayed Outputs take effect on next clock edge propagation delays must exceed hold times Outputs State Time Clock Inputs

Combinational Logic for Circuit Structure State Register (flip-flops) Xi Inputs Comb. Logic for Outputs Combinational Logic for Next State (Flip-Flop Inputs) Zk Outputs Clock State Feedback

Question Is this the only way to build sequential logic circuits? Why bother? The possibility that we might achieve a smaller circuit….

Two Ways to Do It Does the output depend only on the current state or does it also depend on the input? Synchronous Outputs change when the state changes on the clock edge. Asynchronous Outputs change when the input changes. The state changes on the next clock edge. Only the current state  Moore Also the current inputs  Mealy

Combinational Logic for Moore Machine Xi Inputs State Register Comb. Logic for Outputs Combinational Logic for Next State (Flip-Flop Inputs) Zk Outputs Clock State Feedback

Moore Machine State Diagram N+D [1] 15¢ 0¢ 5¢ 10¢ D [0] N D + Reset Reset N D Current state Output N and D Input Causes a State Transition N or D

Outputs depend on both Current State & Inputs Combinational Logic for Mealy Machine Outputs depend on both Current State & Inputs Xi Inputs Zk Outputs Combinational Logic for Next State and Outputs State Register Clock State Feedback

Notation Current State New State Input(s)/Outputs

Mealy Machine State Diagram Reset N D + Reset/0 0¢ N/0 N D/0 5¢ D/0 Current state N/0 Reset/0 D/1 10¢ Input Causes a State Transition N D/0 N+D/1 15¢ Reset/1 Output Note this diagram can be simplified

Comments More vulnerable to glitches Mealy machines associate outputs with transitions (i.e., arrows) Upside: Often, Mealy machines can do the same job with fewer states Downside: An input change can immediately change the output More vulnerable to glitches

Moore vs. Mealy Notation N+D/1 15¢ 0¢ 5¢ 10¢ D/0 N D + Reset/0 Reset/0 Reset/1 N D/0 D/1 Reset N N+D [1] 15¢ 0¢ 5¢ 10¢ D [0] N D + Reset Reset N D

Another Example Consider a machine that asserts its output when the input has 2 or more consecutive 1s 000101010100111010110000

Interpretation of states Moore Machine 0? 1? 11 Interpretation of states 1 2 [0] [1] 0. Last input = 0 1. Last two inputs = 01 2. Last two inputs = 11

Interpretation of states Mealy Machine 0? 1? Interpretation of states 1/0 1 0/0 1/1 0. Last input = 0. Output = 0, for either input 1. Last input = 1. Output = 1 for input =1, Output = 0 for input = 0.

Designers like Mealy, because of the fewer states. Comparison Moore Machine Mealy Machine 1 2 [0] [1] 1/0 1 0/0 1/1 Designers like Mealy, because of the fewer states.

Do Activity #1 Now Moore Machine Mealy Machine 0/0 [0] 1 1/1 1/0 1 2 2 [0] [1] 1/0 1 0/0 1/1

Reverse Engineering Given a circuit, try to figure out what it does and how Good for industrial espionage! Our goal today: Get to know Moore and Mealy machines better by doing some reverse engineering

Mystery Moore Machine Input: X State bits: A & B Output: Z J Q A Input: X State bits: A & B Output: Z Negative edge triggered C X K Q \A \B R \Reset Clock X J Q B = Z C X K Q \B \A R \Reset

The “Signal Trace Method” One Way to Proceed Treat the circuit as a “black box” Feed it lots and lots of input patterns Observe the output patterns Build a table describing state transitions The “Signal Trace Method”

Apply the input sequence 1010101010, and observe the result. Signal Trace Method Apply the input sequence 1010101010, and observe the result. 100 X Clk A Z (= B) \Reset Reset AB = 00 X = 1 = 0 = 1 1 X = 0 = 1 = 10 = 0 = 01 = 0 = 00 = 00 = 1 1 = 10

Partial State Transition Table 1 B X A+ ? B+ Z To see what happens in the ? cases, we need to try more input cases, e.g., 1111.

Signal Trace Method Evaluation This can work nicely on small examples. However, each extra state bit doubles the number of possible states. Also, it can be hard to exercise all states. If we haven’t caused a certain state to occur, is it really unreachable, or should we just try harder? This process collapses on large examples.

Is There a Systematic Way? Figure out the Boolean Functions describing the Next-state and Output(s) The “Function Analysis Method”

Function Analysis Method Determine the Inputs from the combinational logic J C K R Q FFa FFb X \Reset A B = Z \A \B Clk Ja = X Ka = X • B Jb = X Kb = X  A Z = B Derive the next states A+ = Ja • A + Ka • A = X • A + (X + B) • A B+ = Jb • B + Kb • B = X • B + (X  A) • B Now we can find the missing transitions

Fill in Table A 1 B X A+ B+ Z Ja = X Ka = X • B Jb = X Kb = X  A 1 B X A+ B+ Z Ja = X Ka = X • B Jb = X Kb = X  A Z = B A+ = Ja • A + Ka • A = X • A + (X + B) • A B+ = Jb • B + Kb • B = X • B + (X  A) • B

Completed State Transition Table A 1 B X A+ B+ Z 00 01 [0] [1] 1 1 1 11 10 [1] 1 [0] 1 1

Mystery Mealy Machine II D C R Q J K X Clk A B Z \Reset \ DA Input: X State Bits: A & B Output: Z State register consists of a D F/F and a JK F/F

This method is better. Analyze the functions directly. Formal Method This method is better. Analyze the functions directly. E.g., X A B DA A+ = B • (A + X) = A • B + B • X B+ = Jb • B + Kb • B = (A  X) • B + X • B Z = A • X + B • X

State Transition Table 1 B X A+ B+ Z A+ = B • (A + X) = A • B + B • X B+ = Jb • B + Kb • B = (A  X) • B + X • B Z = A • X + B • X

State Diagram A 1 B X A+ B+ Z 0/0 0/1 00 01 1/0 1/1 1/0 11 10 1/1 0/0 1 B X A+ B+ Z 0/1 00 01 1/0 1/1 1/0 11 10 1/1 0/0 0/1

Mealy Machine Notes The inputs to F/F’s must be stable for the setup time before the clock event. The output is valid only on the next negative clock edge - not before, not after. We may latch the output to keep it valid longer.

Synchronous Mealy Machines A Popular Practical Tradeoff Clock Output Latch Clock State Feedback Zk Outputs Xi Inputs State Register Combinational Logic for Outputs and Next State

Do Activity #2 Now For Next Class: Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: Sec 8.5 of Katz, omit the ABEL and ASM descriptions This reading is necessary for getting points in the Studio Activity!