Lecture No. 32 Sequential Logic.

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Presentation transcript:

Lecture No. 32 Sequential Logic

Recap Next-State table Flip-flop transition table Flip-flop input table Karnaugh maps Logical expressions for flip-flop inputs Sequential circuit Implementation

Design of D Sync. Counters Flip-flop transition table (tab 1) Flip-flop input table (tab 2) Karnaugh maps (tab 3) Logical expressions for flip-flop inputs Sequential circuit Implementation (fig 1a) Timing diagram (fig 1b)

Design of Up/Down Counters State Diagram (fig 2) Next-State Table (tab 4) Flip-flop transition table (tab 5) Flip-flop input table (tab 6a, 6b) Karnaugh maps (tab 7a, 7b, 7c) Logical expressions for flip-flop inputs Sequential circuit Implementation (fig 3)

State Reduction State Diagram (fig 4) Input/Output sequence (tab 8) Next-State table reduction (tab 9a, 9b, 9c) Reduced State Diagram (fig 5) Input/Output sequence (tab 10)