Day 3: September 4, 2013 Gates from Transistors ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 4, 2013 Gates from Transistors Penn ESE370 Fall2013 -- DeHon

Previously Simplified models for reasoning about transistor circuits Zeroth-order Penn ESE370 Fall2013 -- DeHon

Today How to construct static CMOS gates Penn ESE370 Fall2013 -- DeHon

Outline Circuit understanding (preclass) Static CMOS Gate function identification Static CMOS Structure Inverter Construct gate Inverting Cascading Penn ESE370 Fall2013 -- DeHon

What function? Buffer Vin=Vdd  Vout=Vdd Vin=0  Vout=0 Penn ESE370 Fall2013 -- DeHon

Why Zeroth Order Useful? Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Make sure understand logical function (achieve logical function) before worrying about performance details Penn ESE370 Fall2013 -- DeHon

What gate? Penn ESE370 Fall2013 -- DeHon

What function? Penn ESE370 Fall2013 -- DeHon

DeMorgan’s Law /f = a + b What is f? Penn ESE370 Fall2013 -- DeHon

What function? Penn ESE370 Fall2013 -- DeHon

Static CMOS Gate Penn ESE370 Fall2013 -- DeHon

Static CMOS Gate Structure Penn ESE370 Fall2013 -- DeHon

Static CMOS Gate Structure Penn ESE370 Fall2013 -- DeHon

Static CMOS Gate Structure Drives rail-to-rail (output is Vdd or Gnd) Inputs connects to gates  load is capacitive Once charge capacitive output, doesn’t use energy (first order) Output actively driven Penn ESE370 Fall2013 -- DeHon

Inverter Out = /in Penn ESE370 Fall2013 -- DeHon

Inverter Penn ESE370 Fall2013 -- DeHon

Why zeroth-order adequate? Static analysis – can ignore capacitors Capacitive loads – resistances don’t matter Feed forward for gates – don’t generally have loops can work forward from known values Logic drive rail-to-rail Don’t have to reason about intermediate voltage levels Penn ESE370 Fall2013 -- DeHon

What zeroth-order not tell us? Delay Dynamics Behavior if not Capacitively loaded Acyclic (if there are Loops) Rail-to-rail drive Penn ESE370 Fall2013 -- DeHon

Gate Design Example Penn ESE370 Fall2013 -- DeHon

Gate Design Design gate to perform: f=(/a+/b)*/c Penn ESE370 Fall2013 -- DeHon

f=(/a+/b)*/c Strategy: Use static CMOS structure Design PMOS pullup for f Use DeMorgan’s Law to determine /f Design NMOS pulldown for /f Penn ESE370 Fall2013 -- DeHon

f=(/a+/b)*/c PMOS Pullup for f? Penn ESE370 Fall2013 -- DeHon

f=(/a+/b)*/c Use DeMorgan’s Law to determine /f. What is /f ? Penn ESE370 Fall2013 -- DeHon

f=(/a+/b)*/c NMOS Pulldown for /f? Penn ESE370 Fall2013 -- DeHon

f=(/a+/b)*/c a c b Penn ESE370 Fall2013 -- DeHon

Static CMOS Source/Drains With PMOS on top, NMOS on bottom PMOS source always at top (near Vdd) NMOS source always at bottom (near Gnd) Penn ESE370 Fall2013 -- DeHon

Inverting Gate Penn ESE370 Fall2013 -- DeHon

Inverting Stage Each stage of Static CMOS gate is inverting Penn ESE370 Fall2013 -- DeHon

How do we buffer? Penn ESE370 Fall2013 -- DeHon

How implement OR? Penn ESE370 Fall2013 -- DeHon

Cascading Stages Penn ESE370 Fall2013 -- DeHon

Stages Can always cascade “stages” to build more complex gates Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality but may not be smallest/fastest/least power Penn ESE370 Fall2013 -- DeHon

Implement: f=a*/b Pullup? Pulldown? Penn ESE370 Fall2013 -- DeHon

f=a*/b Penn ESE370 Fall2013 -- DeHon

Big Idea Systematic construction of any gate from transistors Use static CMOS structure Design PMOS pullup for f Use DeMorgan’s Law to determine /f Design NMOS pulldown for /f Penn ESE370 Fall2013 -- DeHon

Admin Office hours Thursday: HW1 due Friday in Detkin (RCA) Lab Today only: Spencer 7:30—8:30pm Ketterer Monday: Spencer 5-6pm Ketterer Tuesday: Andre 4:15-5:30pm Levine 270 Thursday: HW1 due identify gates; use electric Friday in Detkin (RCA) Lab Please read through HW2, Lab1 details Bring USB drive with you to lab on Friday to store waveforms Penn ESE370 Fall2013 -- DeHon