Day 5: September 17, 2010 Restoration ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 5: September 17, 2010 Restoration Penn ESE370 Fall2010 -- DeHon

Today How do we make sure logic is robust Can assemble into any (feed forward) graph Can tolerate loss and noise ….while maintaining digital abstraction Penn ESE370 Fall2010 -- DeHon

Outline Two problems Cascade failure Restoration Transfer Curves Noise Margins Non-linear Penn ESE370 Fall2010 -- DeHon

Wire Crossings and Shorts Wires connected/shorted Wires not connected Penn ESE370 Fall2010 -- DeHon

Two Problems Output not go to rail Signals may be perturbed by noise Penn ESE370 Fall2010 -- DeHon

Output not go to Rail CMOS, capacitive load CMOS, resistive load? Mostly doesn’t have problem CMOS, resistive load? Igd≠0 ? How close to rail do I need to get? Penn ESE370 Fall2010 -- DeHon

Wire Resistance Penn ESE370 Fall2010 -- DeHon

Wire Resistance Penn ESE370 Fall2010 -- DeHon

Wire Resistance Sanity check Wire twice as long = resistors in series Wire twice as wide = resistors in parallel Penn ESE370 Fall2010 -- DeHon

Wire Resistance 1000 mm long wire? 1 cm long wire? Length of die side? Penn ESE370 Fall2010 -- DeHon

Die Sizes Processor Die Size Transistor Count Process Core 2 Extreme X6800 143 mm² 291 Mio. 65 nm Core 2 Duo E6700 143 mm² 291 Mio. 65 nm Core 2 Duo E6600 143 mm² 291 Mio. 65 nm Core 2 Duo E6400 111 mm² 167 Mio. 65 nm Core 2 Duo E6300 111 mm² 167 Mio. 65 nm Pentium D 900 280 mm² 376 Mio. 65 nm Athlon 64 FX-62 230 mm² 227 Mio. 90 nm Athlon 64 5000+ 183 mm² 154 Mio. 90 nm http://www.tomshardware.com/reviews/core2-duo-knocks-athlon-64,1282-4.html Penn ESE370 Fall2010 -- DeHon

Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall2010 -- DeHon

Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall2010 -- DeHon

IR-Drop Since interconnect is resistive and gates pull current off the supply interconnect The Vdd seen by a gate is lower than the supply Voltage by Vdrop=Isupply x Rdistribute Two gates in different locations See different Rdistribute Therefore, see different Vdrop Penn ESE370 Fall2010 -- DeHon

Output not go to Rail CMOS, capacitive load CMOS, resistive load Mostly doesn’t have problem CMOS, resistive load Due to IR drop, “rails” for two communicating gates may not match Penn ESE370 Fall2010 -- DeHon

Two Problems Output not go to rail Signals may be perturbed by noise Is this tolerable? Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage Penn ESE370 Fall2010 -- DeHon

Noise Sources? What did we see in lab when zoomed in on signal transition? Signal coupling Crosstalk Leakage Ionizing particles IR-drop in signal wiring Penn ESE370 Fall2010 -- DeHon

Two Problems Output not go to rail Signals may be perturbed by noise Is this tolerable? Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage What happens to degraded signals? Penn ESE370 Fall2010 -- DeHon

Preclass All 1’s  logical output? Penn ESE370 Fall2010 -- DeHon

Preclass 1.0 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2010 -- DeHon

Preclass 0.95 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2010 -- DeHon

Degradation Cannot have signal degrade across gates Want to be able to cascade arbitrary set of gates Penn ESE370 Fall2010 -- DeHon

Gate Creed Gates should leave the signal “better” than they found it “better”  closer to the rails Penn ESE370 Fall2010 -- DeHon

Restoration Discipline Define legal inputs Gate works if Vin “close enough” to the rail Restoration Gate produces Vout “closer to rail” Tolerates some drop between out and in Call this our “Noise Margin” Penn ESE370 Fall2010 -- DeHon

Noise Margin Voh – output high Vol – output low Vih – input high Vil – input low NMh = Voh-Vih NMl = Vol-Vil One mechanism, addresses numerous noise sources. Penn ESE370 Fall2010 -- DeHon

Restoration Discipline Define legal inputs Gate works if Vin “close enough” to the rail Vin > Vih or Vin < Vil Restoration Gate produces Vout “closer to rail” Vout < Vol or Vout > Voh Penn ESE370 Fall2010 -- DeHon

Restoring Transfer Function Penn ESE370 Fall2010 -- DeHon

Restoring Transfer Function For multi-input functions, hold non-controlling inputs at Vil, Vih respectively. (relate preclass exercise) Penn ESE370 Fall2010 -- DeHon

Ideal Transfer Function Penn ESE370 Fall2010 -- DeHon

Linear Transfer Function? O=Vdd-A Noise Margin? Penn ESE370 Fall2010 -- DeHon

Non-linearity Need non-linearity in transfer function Could not have built restoring gates with R, L, C circuit Linear elements Penn ESE370 Fall2010 -- DeHon

Transistor Non-Linearity Penn ESE370 Fall2010 -- DeHon

All Gates If hope to assemble design from collection of gates, Voltage levels must be consistent and supported across all gates Penn ESE370 Fall2010 -- DeHon

Admin HW2 is out Monday in Ketterer Wednesday back here Lab combo Penn ESE370 Fall2010 -- DeHon

Big Idea Need robust logic Restoration and noise margins Can assemble into any (feed forward) graph Can tolerate loss and noise ….while maintaining digital abstraction Restoration and noise margins Every gate makes signal “better” Design level of noise tolerance Penn ESE370 Fall2010 -- DeHon