MIPS Assembly.

Slides:



Advertisements
Similar presentations
Review of the MIPS Instruction Set Architecture. RISC Instruction Set Basics All operations on data apply to data in registers and typically change the.
Advertisements

Lecture 5: MIPS Instruction Set
MIPS assembly. Review  Lat lecture, we learnt  addi,  and, andi, or, ori, xor, xori, nor,  beq, j, bne  An array is stored sequentially in the memory.
Systems Architecture Lecture 5: MIPS Instruction Set
Chapter 2 Instructions: Language of the Computer
Chapter 2.
Computer Structure - Computer Arithmetic Goal: Representing Numbers in Binary  Base 10 (decimal) - Numbers are represented using 10 numerals: 0, 1, 2,
Arithmetic CPSC 321 Computer Architecture Andreas Klappenecker.
Computer Architecture CPSC 321 E. J. Kim. Overview Logical Instructions Shifts.
Logical & shift ops (1) Fall 2007 Lecture 05: Logical Operations.
Lecture 5 Sept 14 Goals: Chapter 2 continued MIPS assembly language instruction formats translating c into MIPS - examples.
Arithmetic I CPSC 321 Andreas Klappenecker. Administrative Issues Office hours of TA Praveen Bhojwani: M 1:00pm-3:00pm.
ECE 4436ECE 5367 ISA I. ECE 4436ECE 5367 CPU = Seconds= Instructions x Cycles x Seconds Time Program Program Instruction Cycle CPU = Seconds= Instructions.
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Hao Ji.
CS 300 – Lecture 6 Intro to Computer Architecture / Assembly Language Instructions.
MIPS assembly. Computer What’s in a computer? Processor, memory, I/O devices (keyboard, mouse, LCD, video camera, speaker), disk, CD drive, …
CMPE 325 Computer Architecture II Cem Ergün Eastern Mediterranean University Integer Representation and the ALU.
Computer Engineering AddSub page 1 Basic Building Blocks Multiplexer + Demultiplexer Adder.
Registers and MAL Lecture 12. The MAL Architecture MAL is a load/store architecture. MAL supports only those addressing modes supported by the MIPS RISC.
1. 2 Instructions: Words of the language understood by CPU Instruction set: CPU’s vocabulary Instruction Set Architecture (ISA): CPU’s vocabulary together.
CSCI 136 Lab 1: 135 Review.
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /08/2013 Lecture 10: MIPS Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE CENTRAL STATE.
MIPS coding. Review Shifting – Shift Left Logical (sll) – Shift Right Logical (srl) – Moves all of the bits to the left/right and fills in gap with 0’s.
Computer Organization Instructions Language of The Computer (MIPS) 2.
Computer Organization CS224 Fall 2012 Lessons 7 and 8.
Computer Architecture Lecture 9 MIPS ALU and Data Paths Ralph Grishman Oct NYU.
Addition, Subtraction, Logic Operations and ALU Design
Chapter 2 — Instructions: Language of the Computer — 1 Memory Operands Main memory used for composite data – Arrays, structures, dynamic data To apply.
CMPUT Computer Organization and Architecture I1 CMPUT229 - Fall 2003 Topic6: Logic, Multiply and Divide Operations José Nelson Amaral.
MIPS Instruction Set Architecture Prof. Sirer CS 316 Cornell University.
COM181 Computer Hardware Lecture 6: The MIPs CPU.
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Yaohang Li.
CS2100 Computer Organisation
Computer Architecture & Operations I
Computer Architecture & Operations I
COMPUTER ARCHITECTURE & OPERATIONS I
Morgan Kaufmann Publishers
Lecture 4: MIPS Instruction Set
Computer Organization and Design Instruction Sets - 2
Assembly Programming using MIPS R3000 CPU
MIPS Assembly.
Lecture 4: MIPS Instruction Set
MISP Assembly.
MIPS assembly.
Computer Architecture & Operations I
MIPS Instruction Encoding
ECE232: Hardware Organization and Design
MIPS Instruction Encoding
Chapter 2 Instructions: Language of the Computer
Instruction encoding The ISA defines Format = Encoding
Computer Architecture
Basic Building Blocks Multiplexer Demultiplexer Adder +
Instruction encoding The ISA defines Format = Encoding
COMP541 Datapaths I Montek Singh Mar 18, 2010.
UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2018
Instruction encoding The ISA defines Format = Encoding
COMS 361 Computer Organization
Basic Building Blocks Multiplexer Demultiplexer Adder +
MIPS Instruction Set Architecture
Assembly Programming using MIPS R3000 CPU
MIPS Assembly.
Instruction encoding The ISA defines Format = Encoding
MIPS assembly.
MIPS Assembly.
7/6/
MIPS Processor.
9/13/
MIPS instructions.
MIPS Assembly.
CS/COE0447 Computer Organization & Assembly Language
Presentation transcript:

MIPS Assembly

Review A computer has processor, memory, and IO devices. The processor stores values in registers, and modifies values by sending them to the ALU. Memory is where the computer stores a large number of values. Every byte can be accessed by specifying a unique address. The address goes from 0 to 0xffffffff in MIPS. In MIPS we mainly work with word which is 4 bytes. MIPS instructions learned: add, sub. lw, sw.

Constant or Immediate Operands 1/17/2019 Constant or Immediate Operands Many times we use a constant in an operation For example, i++, i--, i += 4, and so on Since constant operands occur frequently, we should include constants inside arithmetic operations so that they are much faster MIPS has an add instruction that allows one operand to be a constant The constant must be in 16 bits, as a signed integer in 2’s complement format addi $s1, $s2, 100 # $s1 = $s2 + 100 1/17/2019 CDA3100 CDA3100

1/17/2019 Logical Operations Often we need to operate on bit fields within a word. Which allow us to pack and unpack bits into words and perform logical operations such as logical and, logical or, and logical negation 1/17/2019 CDA3100 CDA3100

Bit-wise AND Apply AND bit by bit 1/17/2019 Bit-wise AND Apply AND bit by bit The resulting bit is 1 if both of the input bits are 1 and zero otherwise and $t2, $t0, $t1 There is also a version of AND with an immediate andi $t2, $t1, 12 The immediate is treated as an unsigned 16-bit number Ex: $t0 <- 00001100 $t1 <- 00000110 $t2 <- 00000100 1/17/2019 CDA3100 CDA3100

Bit-wise OR Apply OR bit by bit 1/17/2019 Bit-wise OR Apply OR bit by bit The resulting bit is 1 if at least one of the input bits is 1 and zero otherwise or $t2, $t0, $t1 There is also a version of OR with an immediate ori $t2, $t1, 12 The immediate is treated as an unsigned 16-bit number Ex: $t0 <- 00001100 $t1 <- 00000110 $t2 <- 00001110 1/17/2019 CDA3100 CDA3100

Bit-wise XOR Apply XOR bit by bit 1/17/2019 Bit-wise XOR Apply XOR bit by bit The resulting bit is 1 if two bits are different xor $t2, $t0, $t1 There is also a version of OR with an immediate xori $t2, $t1, 12 The immediate is treated as an unsigned 16-bit number Ex: $t0 <- 00001100 $t1 <- 00000110 $t2 <- 00001010 1/17/2019 CDA3100 CDA3100

1/17/2019 NOR Since NOT takes one operand and results in one operand, it is not included in MIPS as an instruction Because in MIPS each arithmetic operation takes exactly three operands Instead, NOR is included The resulting bit is 0 if at least one of the input bits is 1 nor $t2, $t0, $t1 How to implement NOT using NOR? Using $zero as one of the input operands It is included in MIPS as a pseudoinstruction Ex1 (NOT): $t0 <- 00001100 $t1 <- 00000000 $t2 <- 11110011 Ex2 (NOR): $t1 <- 00000110 $t2 <- 11110001 1/17/2019 CDA3100 CDA3100

Exercise 1 How can we load an integer value (like 100) into a register ($t0)?

Exercise 1 How can we load an integer value (like 100) into a register ($t0)? addi $t0, $zero, 100 ori $t0, $zero, 80 Which should we prefer? ori. Because it is simpler than add. Simpler means less time, less power consumption.