ADC External RAM Config (4x1Mbit) EPROM Front LEDs LED Controller Box FE Connectors (1-24) Front LEDs SCA_CLK ADC CLK FE Control Signals Data In[215..0] A[5..0] FE Control Signals LED Controller Box Calibration Box Reset Box FPGA CLK (50MHz) ADC FPGA CLK PLL2 Out FIFO PLL1 TPC CLK (25MHz) 2*TPC CLK 4*TPC CLK LVDS CLK(68,75MHz) Controller Box Read Box Compressing Box Sending Controller Box Read Con1[7..0] Connector FIFOs (1-24) Pad-Row Builder Zero Counter Header Builder Con2[7..0] Event Gate Read Ok Pedestal Substraction PM Data[8..0] CLK Con24[7..0] Data or Status Serialiser Data[8..0] Out FIFO Data Write Pedestal Pedestal Out[192..0] Pedestal In[191..0] Read Pedestal Upload Pedestal[8..0] Working Parameters[39..0] Pedestal Box FW Update Box Upload FW[8..0] Receiver Box External RAM (4x1Mbit) D[63..0] Pedestal Out FIFO Config EPROM Out FIFO Command and Status Decoder A[15..0] CLK WEn In FIFO Deserialiser Pedestal In FIFO Download FW[32..0] Data REn Data Decoder Download Pedestal[32..0]

Reset Box Prepare clocks for modules Prepare delayed reset for modules TPC_CLKx2 (50 MHz) for Controller Box, Read Box and Pedestal Box TPC_CLKx4 (100 MHz) for Controller Box TPC_CLKx10 (250 MHz) for Controller Box LVDS_CLK (68,75 MHz) for Sending Controller Box and Compressing Box ASMI_CLK (20 MHz) for Firmware Update Box MB_CLK (50 MHz) for Controller Box, Calibration Box and LED Controller Box Prepare delayed reset for modules

Reset Box Clock Box PLL1 PLL2 FPGA_CLK (50 MHz) TPC_CLK (25 MHz) FPGA_Power_Good Soft_Reset TPC_CLKx2 TPC_CLKx4 TPC_CLKx10 MB_CLK LVDS_CLK ASMI_CLK Reset Signals PLL1 PLL2 Reset Counter

Controller Box Prepare clock signals for Front-End cards SCA CLK for shift register write and read (5 MHz or 10 MHz) ADC CLK for ADC read-out (12,5 MHz) Prepare control signals for Front-End cards Shift register control signals Amplifier control signals ADC control signals Prepare the Busy signal Prepare the Trigger Counter Read and evaluate the Working Parameter register

Controller Box Timer Box Reset TPC_CLKx4 (100 MHz) FPGA_CLK (50 MHz) TPC_CLKx2 (50 MHz) Timer Box Write Controller SCA CLK SCA_CLK ADC_CLK ADC CLK PreAmp_En WriteRead Reset_ShiftReg Analog_Reset ADC_Reset ADC_Load_Buffer Read Data FE_Command_Read Read_OK Event_OK FE_Command_Read_Req Trigger End_Of_Data_Block Working_Parameters Trigger LED Trigger_Counter[31..0] Trigger_LED MB_Busy Trigger Counter Busy

Read Box Prepare Address signals for Front-End cards ADC_OE for select the Front-End cards A[5..0] for addressing the ADCs Read the Front-End data Read Pedestal for correction of Front-End data Make Pedestal and threshold subtraction Store the corrected Front-End data in the Connector FIFOs Write the Front-End data to the External Memory Read and evaluate the Working Parameter register

Read Box FIFO FIFO Reset Addressing TPC_CLKx2 (50 MHz) A[5..0] ADC_OE Read_Data Read_Ok_Ack Pedestal_Memory_Ready Addressing A[5..0] ADC_OE Read_OK Event_OK Pedestal_Request Read_Pedestal Read FIFO Con_FIFO_Data[7..0] Con_FIFO_Read D_In[215..0] FIFO Data_Strobe Write_Pedestal Pedestal_Mem_In[191..0] Pedestal_Mem_Out[191..0] Jumper_Settings Working_Parameters

Front-End read out sequences Write: 20,5us Read: 11,7ms Time Trigger Read 1. time slice Read 2. time slice Read 3. time slice Read 256. time slice Analog Reset: 5,6us Set Amplifiers: 10us Analog to Digital Conversion: 20us Data Read-out (2x32 ch.): 10,2us Read Data from FE1 Channel 1 Read Data from FE1 Channel 2 Read Data from FE1 Channel 32 Read Data from FE2 Channel 32

Read: 23,5ms ((5,6us+10us+20us+10,2us)*512) Front-End read-out timing Write: 41us (512*80ns) Read: 23,5ms ((5,6us+10us+20us+10,2us)*512) Analog Reset 10us Set Ampl. 10us Analog to Digital Conv. 20us (256 ADC cycles) Read Card 1-2 2*5,1us Analog Reset 5,6us Set Ampl. 10us Analog to Digital Conv. 20us (256 ADC cycles) PA_Enable/Reset Write/Read Reset_Shift_Reg Analog_Reset SCA_CLK (512 cycles) ADC_Reset ADC_Load_Buffer ADC_OE1 ADC_OE2 Connector 1 1.Data Out 2.Data Out Connector 2 1.Data Out 2.Data Out Connector 24 1.Data Out 2.Data Out ADC_CLK

Compressing Box Read the Connector FIFOs Build data in Ped-row order Make the zero compression Add Mini Header to top of the data. Store the compressed data in the Out FIFO Store the compressed data in the External Memory, if Out FIFO full Read and evaluate the Working Parameter register

Compressing Box FIFO Reset LVDS CLK (68,75 MHz) Controller Read_OK Read_OK_Ack Out_FIFO_Data[8..0] Out_FIFO_Read FIFO Zero Compressor Con_FIFO_Data[7..0] Con_FIFO_Read Event_OK Event_Processed_Ack Event_Processed External Memory Writer SRAM_FIFO_Write SRAM_FIFO_Data[64..0] FE_Command_Read Trigger_Counter Jumper_Settings Working_Parameters FE_Command_Read_Req

Read-out order of SR sector FIFO Con1A FIFO Con1B FIFO Con2A FIFO Con2B FIFO Con12A FIFO Con12B Multiplexer Pad-row table   Connector FIFO numbers Pad-row 1 2B 6B 8B 12B Pad-row 2 2A 6A 8A 12A Pad-row 3 1B 5B 7B 11B Pad-row 4 1A 5A 7A 11A Pad-row 5 4B 3B 10B 9B Pad-row 6 4A 3A 10A 9A

Read-out order of HR sector FIFO Con1A FIFO Con1B FIFO Con2A FIFO Con2B FIFO Con12A FIFO Con12B Multiplexer Pad-row table   Connector FIFO numbers Pad-row 1 2A 4A 6A 8A 10A 12A Pad-row 2 Pad-row 3 1A 3A 5A 7A 9A 11A Pad-row 4

Out FIFO data structure Lasd Data [8] Data type [7..0] Mini Header 1. byte Mini Header 2. byte Mini Header 3. byte Mini Header 4. byte Event Data 1. byte Event Data 2. byte Event Data n. byte 1 Event Data last byte

Ch N. Ch 1. 32x Write Controller Box Channel Chooser Box Command Send Data Reader Status Req. Send Transmitter Box CLK Busy Signal Serialiser Data[7..0] Data Read and Send Data Status Ansver[31..0] XOFF SIU Interface Receiver Box Read Controller Box SIU Out FIFO Command and Status Decoder DataN[31..0] Packet and Header Builder CLK Deserialiser Data In FIFO Data Decoder Data[31..0] SIU Data[31..0] 32x SIU Controls Read Out Controller Ch 1. Write Controller Box Command Send SIU In FIFO Status Req. Send Transmitter Box CLK Command Register Serialiser Data[7..0] Data Read and Send Data Status Reader Status Ansver[31..0] XOFF Status Register Receiver Box Read Controller Box Command and Status Decoder Data1[31..0] Packet and Header Builder CLK Deserialiser Clock Box Data In FIFO Data Decoder Data[31..0] 50MHz