Upset Susceptibility and Design Mitigation of PowerPC405 Processors Embedded in Virtex II-Pro FPGAs Gary Swift Jet Propulsion Laboratory / California Institute of Technology Gregory Allen JPL Sana Rezgui Xilinx Fayez Chayab MDA Jeff George The Aerospace Corporation Carl Carmichael Xilinx Swift 1

Background - Reconfigurable FPGA Upsets The basic building blocks are soft to upset [Ref. 1] Thus, critical applications require both triple modular redundancy (TMR) and configuration scrubbing Swift 2

Embedded “Hard-Core” Processor(s) Upset PowerPC 405 cores in Virtex II-Pro family FPGAs offer unprecedented computational power inside an FPGA, but include additional upsetable storage elements Swift 3

Processor Upsets – Data Cache Processor caches are very important features for increased performance; however, upsets in the caches can lead to system errors. Swift 4

One-Chip Solution: Lockstep 1F2P [Ref. 2] Swift 5

Two-Chip Solution: Pair of Locksteps 2F4P Swift 6

Three-Chip Solution: Rad-hard Arbiter 3F+3P [Ref. 3] Swift 7

Comparison No mitigation 1-chip 2-chip 3-chip Daily upsets, no error detection Daily brief outages to re-boot 10s of yrs between re-syncs Hundreds of years ?? SIMPLEST Lockstep IP (inside FPGA) MOST BRUTE FORCE 1x 2.5x 5x 4x Error Robustness Design Complexity Power Consumption Board Area Swift 8

References [1] J. George et al., “Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA,” Paper 211, MAPLD 2005. [2] M. Wang and G. Bolotin, “SEU Mitigation Techniques for Xilinx Virtex-II Pro FPGA,” Paper D110, MAPLD 2004, http://klabs.org/mapld04/presentations/session_d/ 1_d110_wang_s.ppt [3] J. Lyke and B. Marty, Virtual Field Programmable Gate Array Triple Modular Redundant Cell Design, Air Force Research Laboratory: Space Vehicles Directorate, AFRL-VS-PS-TR-2004-1093, April 28, 2004. Swift 9