Delphi Confidential Precision Bump Formation Mushroom type bump X-Sec laser ablate plated up bump Fabrication process.

Slides:

Advertisements

Similar presentations

EXPLORING QUANTUM DOTS

Advertisements

Step-by-Step Column Design Designing a 10-column spread.

SMG facility – 24k Square Feet. Drilling We have 7 fully automated Excellon Drilling/ Routing machines. The drilling program is generated from the customer.

Printed Wiring Board Fabrication. Imaging For feature sizes less than 200μm, use photolithography process 1.Clean surface 2.Apply photoresist 3.Expose.

CCTC MFG Capabilities & Technology Roadmap

Sierra Proto Express Introducing our Micro Electronics Division.

EELE 461/561 – Digital System Design

Background and Capabilities Presentation : Elreha GmbH was established in Hockenheim, Germany, designing and manufacturing temperature controls.

Opportunities for Gigascale Integration in Three Dimensional Architectures James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics.

HV-CMOS Hybridization

Design Guidelines Conductors Metallized Holes Via Fills Resistors Substrates Layout Material Properties Data Formats PHOTO NEEDED.

Advanced Manufacturing Choices

Recent achievements and projects in Large MPGDs Rui de Oliveira 21/01/2009 RD51 WG1 workshop.

Breadboarding and Electronic Components. What is a Breadboard? Sometimes called a proto-board Reusable platform for temporarily built electronic circuits.

ECE/ChE 4752: Microelectronics Processing Laboratory

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.

Mar KOLON Electronic Materials B.C. TDS (Technical Data Sheet) KP-2100.

Solid State Detectors-2

Top Side Conductor vacuum deposition Aluminum sputter deposit in Argon plasma CVC 601-sputter deposition tool.

Printed Circuit Board Design

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

LSU 06/04/2007Electronics 81 CAD Tools for Circuit Design Electronics Unit – Lecture 8 Schematic Diagram Drawing Etched Circuit Board Layout Circuit Simulation.

Read-out boards Rui de Oliveira 16/02/2009 RD51 WG1 workshop Geneva.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip Chip/Bumping Process at VTT Last modified March 16, 2007 By Jaakko.

1/20 Passive components and circuits - CCP Lecture 13.

Lecture on Integrated Circuits (ICs)

Click to edit Master subtitle style 4/25/12 Thermal Management By using PLPCB technology with HEAVY Copper in PCB Pratish Patel CEO, Electronic Interconnect.

AM test sample. outside 20 mm inside 19 mm wallthickness 1 mm height features 4 mm.

II-Lithography Fall 2013 Prof. Marc Madou MSTB 120

— Test board for CBM01B2 baby detectors — Anton Lymanets & Johann Heuser CBM collaboration meeting GSI, 27 February 2008 Microstrip detector testing at.

EST-DEM R. De Oliveira 20 Dec., ‘04 Production of Gaseous Detector Elements  History of Gas Detectors in Workshop  Fabrication of GEM Detectors  Fabrication.

Structural and Thermal Calculation for Recuperative Heat Exchanger Recuperative Heat Exchanger Presented by -- Jinying Zhu.

Silicon /pcb assembly R Thompson, J Freestone LAL 3 June 08.

Trace connecting two pads! More than 45 degree bends Traces too close together Rule of thumb: traces at least 40 mil apart.

Basic Electrical Circuit Materials Colts Neck High School Applied Technology.

Project Update June 22, 2006 ME342A. Project Goal Design a bioMEMs substrate to apply and measure electromechanical forces in the differentiation of human.

IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.

Technology Road Map Imaging And Etching Trace / Space Outers * Current

Givi Sekhniaidze1 CERN, 25 March Givi Sekhniaidze2 The angles for the chambers are: LM1 – ° LM2 – 7.224° SM1 – ° SM2 – ° Do we.

Drawing With Lines and Shapes!

ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.

Low Mass Rui de Oliveira (CERN) July

IPC In-Circuit Test Fixtures In-circuit test fixtures are commonly called bed-of-nails fixtures. A bed-of- nails fixture is a device with.

1 The Math of Printing & Imaging Copyright © Texas Education Agency, All rights reserved. Images and other multimedia content used with permission.

The Development of the Fabrication Process of Low Mass circuits Rui de Oliveira TS-DEM.

LITHOGRAPHY IN THE TOP-DOWN PROCESS - BASICS

TYPE 1 HDI Boards Design Rule

 A PCB is printed circuit board, also known as a printed wiring board. It is used in electronics to build electronic devices. A PCB serves 2 purposes.

Antenna Project in Cameron clean room Wafer preparation, conductor deposition, photolithography.

Definition History Fabrication process Advantages Disadvantages Applications.

Equipment and technological processes for manufacturing GaAs MMICs LITHOGRAPHY ONE TALK 3 1.

IC Manufactured Done by: Engineer Ahmad Haitham.

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.

Printed Circuit Board Design

Mask Design for Molds.

Geometric Design Rules

Wicking: Requirements

積體電路元件與製程半導體物理半導體元件 PN junction CMOS 製程.

Aspiring Medical Proffessionals (AMP)

What determines impedance ?

Lithography Layout, Mask, photo.

Codification of Flip Chip Knowledge

LITHOGRAPHY Lithography is the process of imprinting a geometric pattern from a mask onto a thin layer of material called a resist which is a radiation.

Use the Chain Rule to find {image} {image}

Mask Design for Molds.

Helical antenna It is a simple Broad band VHF and UHF antenna. The concept of Helical antenna is first introduced by J.D.Kraus. It consists of a helix.

Presentation transcript:

Delphi Confidential Precision Bump Formation Mushroom type bump X-Sec laser ablate plated up bump Fabrication process

Delphi Confidential –Simultaneous Laser Operation »Define dot location »Define alignment hole location »Position tolerance +/-.002 w b h h = bump height in. b = bump base w + h w = bump opening 6,8,10 mils The bump is plated within and above the coverlay material. Precision Bump Formation Mushroom type bump Design considerations (dot to dot spacings)

Delphi Confidential Precision Bump Formation Mushroom type bump Examples of mushroom type bump parts For military and commercial applications

Delphi Confidential Photolithography Bump Formation Photoresist defined bump Laminate Photoresist Photo / Develope Plating Strip Photoresist Fabrication process The shape of the bump is controlled by the photoresist image, so various shapes can be defined. Typically used with larger or gross opening in the coverlay Bump heights are in. Bump Widths are in. smaller than the trace widths

Delphi Confidential Photolithography Bump Formation Photoresist defined bump Examples of mushroom type bump parts For military and commercial applications

Delphi Confidential Precision Bump Formation Etch-a-dot type bump Laminate coverlay Laser coverlay openings Plasma Clean openings Plate mushroom bump Etch smaller bump tip On mushroom bump Fabrication process The bump is plated within and above The coverlay surface.

Delphi Confidential Precision Bump Formation Etch-a-dot type bump Examples of mushroom type bump parts For military and commercial applications Typical bump dimensions

Delphi Confidential Typical Gold dot circuit layout Circuit Trace Capabilities:.0025/. 0025[0.0635/0.0635] Width/ Space Calculating Contact Pitch: For Column Pitch: Pcolumn=(No rows-1) x (Trace width) + Base Pad Dia + (No Rows) x Conductor Spacing Bump Height*Bump Base Diameter Bump Base Pad Diameter.0045[0.114].008[0.216].0145[0.368] Column of Contacts Rows of Contacts Circuit Trace Bump Base Bump Base Pad

Delphi Confidential Precision Bump Formation Typical Performance Characteristics Rated current per dot1 amp room temp Contact Resistance<10mOhms Contact Force0-150 gms per contact Vibration10 G max. peak, Hz Mechanical shock30 G, 294 m/s peak Accel. 11 ms duration Operating temp.-40 to +125 C, continuous Bump contact Au Plated over Nickel and Copper Mating surfaceImmersion/hard gold & solder