JANAKIRAMAN E G S PILLAY ARTS AND SCIENCE COLLAGE NAGAPATTINAM DEPARTMENT OF PHYSICS

  The 8 bit CPU with Registers A and B   Internal ROM 4KB   16-bit program counter(PC) and data pointer(DPTR)   Internal RAM of 128 bytes   8-bit Program Status word(PSW)   Two 16 bit Counter / timers   4 eight-bit ports   3 internal interrupts and 2 external interrupts.   Control register   Oscillator and clock circuits.

DPTR- Data Pointer register. DPH,DPL- program counter higher and lower bytes PSEN- program store enable

  CPU REGISTERS:  - ACC : Accumulator.  - B : B register.  - PSW : Program Status Word.  - SP : Stack Pointer.  - DPTR : Data Pointer (DPH, DPL).   INTERRUPT CONTROL:  - IE : Interrupt Enable.  - IP : Interrupt Priority.   I/O PORTS:  - P0 : Port 0.  - P1 : Port 1.  - P2 : Port 2.  - P3 : Port 3.

  TIMERS:  - TMOD : Timer mode.  - TCON : Timer control.  - TH0 : Timer 0 high byte.  - TL0 : Timer 0 low byte.  - TH1 : Timer 1 high byte.  - TL1 : Timer 1 low byte.   SERIAL I/O:  - SCON : Serial port control.  - SBUF : Serial data registers.   OTHER:  PCON : Power control  FOUR 8-BIT I/O PORTS.  Port 0  Port 1  Port 2  Port 3  - MOST HAVE ALTERNATE FUNCTIONS.  - QUASI-BIDIRECTIONAL:

  The 8051 contains 34 general purpose or working registers. Two of these Register A and B.   The immediate result is stored in the accumulator register (Acc) for next operation.   The B register is a register just for multiplication and division operation which requires more register spaces for the product of multiplication and the quotient and the remainder for the division.

  The PSW contain the math flags, User program flag F0,and the register select bits that identify which of the four General-purpose register banks is currently in use by the program.   The math flags include carry(c),auxiliary carry(AC),overflow(OV) and parity(p)

 The 8051 requires an external oscillator circuit. The oscillator circuit usually runs around 12MHz. The crystal generates 12M pulses in one second.   A machine cycle is minimum amount time must take by simplest machine instruction   An 8051 machine cycle consists of 12 crystal pulses (clock cycle).   The first 6 crystal pulses (clock cycle) is used to fetch the Opcode and the second 6 pulses are used to perform the operation on the operands in the ALU.   This gives an effective machine cycle rate at 1MIPS (Million Instructions Per second). The program counter points to the address of the next instruction to be Executed   As the CPU fetches the opcode from the program ROM,the program counter is increasing to point to the next instruction.   The program counter is 16 bits wide   This means that it can access program addresses 0000 to FFFFH, a total of 64K bytes of code

  The data pointer is 16 bit register.   It is used to hold the address of the data in the memory.   The DPTR register can be accessed separately as lower eight bit(DPL) and higher eight bit (DPH).   It can be used as a 16 bit data register or two independent data register.   The stack is a section of RAM used by the CPU to store information temporarily   This information could be data or an address   ‰ The register used to access the stack is called the SP (stack pointer) register   The stack pointer in the 8051 is only 8 bit wide.

Pins 1 – 8 (PORT 1): Pins 1 to 8 are the PORT 1 Pins of PORT 1 Pins consists of 8 – bit bidirectional Input / Output Port with internal pull – up resistors. In older 8051 Microcontrollers, PORT 1 doesn’t serve any additional purpose but just 8 – bit I/O PORT. In some of the newer 8051 Microcontrollers, few PORT 1 Pins have dual functions. P1.0 and P1.1 act as Timer 2 and Timer 2 Trigger Input respectively. P1.5, P1.6 and P1.7 act as In-System Programming Pins. Pin 9 (RST): Pin 9 is the Reset Input Pin. It is an active HIGH Pin i.e. if the RST Pin is HIGH for a minimum of two machine cycles, the microcontroller will be reset. During this time, the oscillator must be running. Pins 10 – 17 (PORT 3): Pins 10 to 17 form the PORT 3 pins of the 8051 Microcontroller. PORT 3 also acts as a bidirectional Input / Output PORT with internal pull-ups. Additionally, all the PORT 3 Pins have special functions. The following table gives the details of the additional functions of PORT 3 Pins.

PORT 3 PinFunctionDescription P3.0RXDSerial Input (receive data) P3.1TXDSerial Output(transmit data) P3.2INT0External Interrupt 0 P3.3INT1External Interrupt 1 P3.4T0Timer 0 P3.5T1Timer 1 P3.6WRExternal Memory Write P3.7RDExternal Memory Read PORT 3 PIN CONFIGURATIONS

Pins 18 & 19: Pins 18 and 19 i.e. XTAL 2 and XTAL 1 are the pins for connecting external oscillator. Generally, a Quartz Crystal Oscillator is connected here. Pin 20 (GND): Pin 20 is the Ground Pin of the 8051 Microcontroller. It represents 0V and is connected to the negative terminal (0V) of the Power Supply. Pins 21 – 28 (PORT 2): These are the PORT 2 Pins of the 8051 Microcontroller. PORT 2 is also a Bidirectional Port i.e. all the PORT 2 pins act as Input or Output. Additionally, when external memory is interfaced, PORT 2 pins act as the higher order address byte. PORT 2 Pins have internal pull-ups. Pin 29 (PSEN): Pin 29 is the Program Store Enable Pin (PSEN). Using this pins, external Program Memory can be read. Pin 30 (ALE/PROG): Pin 30 is the Address Latch Enable Pin. Using this Pins, external address can be separated from data (as they are multiplexed by 8051).During Flash Programming, this pin acts as program pulse input (PROG).

Pin 31 (EA/VPP): Pin 31 is the External Access Enable Pin i.e. allows external Program Memory. Code from external program memory can be fetched only if this pin is LOW. For normal operations, this pins is pulled HIGH. During Flash Programming, this Pin receives 12V Programming Enable Voltage (VPP). Pins 32 – 39 (PORT 0): Pins 32 to 39 are PORT 0 Pins. They are also bidirectional Input / Output Pins but without any internal pull-ups. Hence, we need external pull-ups in order to use PORT 0 pins as I/O PORT. In addition to acting as I/O PORT, PORT 0 also acts as lower order address/data bus when external memory is accessed. Pin 40 (VCC): Pin 40 is the power supply pin to which the supply voltage is given (+5V).

8051 MICROCONTROLLER BASIC CIRCUIT

 Pins 40 (VCC ) and 20 and (GND) are connected to +5V and GND respectively.  A logic HIGH (+5V) on Reset Pin for a minimum of two machine cycles (24 clock cycles) will reset the 8051 Microcontroller  The reset circuit of the 8051 Microcontroller consists of a capacitor, a resistor and a push button and this type of reset circuit provides a Manual Reset Option. If you remove the push button, then the reset circuit becomes a Power-On Reset Circuit.  A Quartz Crystal Oscillator is connected across XTAL1 and XTAL2 pins i.e. Pins 19 and 18. The capacitors C1 and C2 can be selected in the range of 20pF to 40pF.  PORTS 1, 2 and 3, all have internal pull – ups and hence can be directly used as Bidirectional I/O Ports  a 1KΩ Resistor Pack of 8 Resistors is used as a Pull – up for the PORT

8051 MEMORY ORGANIZATION  The 8051 microcontroller's memory is divided into Program Memory and Data Memory. Program Memory (ROM) is used for permanent saving program being executed, while Data Memory (RAM) is used for temporarily storing and keeping intermediate results and variables. Program Memory (ROM) Program Memory (ROM) is used for permanent saving program (CODE) being executed. The memory is read only. Depending on the settings made in compiler, program memory may also used to store a constant variables. The 8051 executes programs stored in program memory only. code memory type specifier is used to refer to program memory.constantcode  8051 memory organization alows external program memory to be added. How does the microcontroller handle external memory depends on the pin EA logical state.

External Data Memory Access to external memory is slower than access to internal data memory. There may be up to 64K Bytes of external data memory. Several 8051 devices provide on-chip XRAM space that is accessed with the same instructions as the traditional external data space XRAM space is typically enabled via proper setting of SFR register and overlaps the external memory space Setting of that register must be manualy done in code, before any access to external memory or XRAM space is made SFR Memory The 8051 provides 128 bytes of memory for Special Function Registers (SFRs)

TIMER1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and TH1.

TMOD (timer mode) Register: This is an 8-bit register which is used by both timers 0 and 1 to set the various timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the upper 4 bits are set aside for timer1. In each case, the lower 2 bits are used to set the timer mode and upper 2 bits to specify the operation.

In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting and stopping. Some timers do this by software, some by hardware, and some have both software and hardware controls. The hardware way of starting and stopping the timer by an external source is achieved by making GATE=1 in the TMOD register. And if we change to GATE=0 then we do no need external hardware to start and stop the timers. The second bit is C/T bit and is used to decide whether a timer is used as a time delay generator or an event counter. If this bit is 0 then it is used as a timer and if it is 1 then it is used as a counter. In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0 respectively. These are used to select the timer mode.

M0 M1 Mode Operating Mode bit timer mode, 8-bit timer/counter THx and TLx as 5-bit prescalar bit timer mode, 16-bit timer/counters THx and TLx are cascaded; There are no prescalar bit auto reload mode, 8-bit auto reload timer/counter; THx holds a value which is to be reloaded into TLx each time it overflows Spilt timer mode. MODE0 Mode 0 is exactly same like mode 1 except that it is a 13-bit timer instead of 16-bit. The 13- bit counter can hold values between 0000 to 1FFFH in TH-TL. Therefore, when the timer reaches its maximum of 1FFH, it rolls over to 0000, and TF is raised.

MODE 1 IT IS A 16-BIT TIMER; therefore it allows values from 0000 to FFFFH to be loaded into the timer’s registers TL and TH. After TH and TL are loaded with a 16-bit initial value, the timer must be started. “SETB TR0” for timer 0 and “SETB TR1” for timer 1. After the timer is started. It starts count up until it reaches its limit of FFFFH. When it rolls over from FFFF to 0000H, it sets high a flag bit called TF (timer flag). This timer flag can be monitored. When this timer flag is raised, one option would be stop the timer with the instructions “CLR TR0“ or CLR TR1 for timer 0 and timer 1 respectively. Again, it must be noted that each timer flag TF0 for timer 0 and TF1 for timer1. After the timer reaches its limit and rolls over, in order to repeat the process the registers TH and TL must be reloaded with the original value and TF must be reset to 0.

Mode 2 It is an 8 bit timer that allows only values of 00 to FFH to be loaded into the timer’s register TH. After TH is loaded with 8 bit value, the 8051 gives a copy of it to TL. Then the timer must be started. It is done by the instruction “SETB TR0” for timer 0 and “SETB TR1” for timer1. This is like mode 1. After timer is started, it starts to count up by incrementing the TL register. It counts up until it reaches its limit of FFH. When it rolls over from FFH to 00. It sets high the TF (timer flag). If we are using timer 0, TF0 goes high; if using TF1 then TF1 is raised. When Tl register rolls from FFH to 00 and TF is set to 1, TL is reloaded automatically with the original value kept by the TH register. To repeat the process, we must simply clear TF and let it go without any need by the programmer to reload the original value. This makes mode 2 auto reload, in contrast in mode 1 in which programmer has to reload TH and TL.

MODE3 Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed to be in mode 0, 1 and 2 independently of similar mode for other timer. This is not true for mode 3; timers do not operate independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3 causes it to stop counting; the control bit TR1 and the timer 1 flag TF1 are then used by timer0.

7TF1 Timer1 over flow flag. Set when timer rolls from all 1s to 0. Cleared When the processor vectors to execute interrupt service routine Located at program address 001Bh. 6TR1 Timer 1 run control bit. Set to 1 by programmer to enable timer to count; Cleared to 0 by program to halt timer. 5 TF0 Timer 0 over flow flag. Same as TF1. 4 TR0 Timer 0 run control bit. Same as TR1. 3 IE1 External interrupt 1 Edge flag. Not related to timer operations. 2 IT1 External interrupt1 signal type control bit. Set to 1 by program to Enable external interrupt 1 to be triggered by a falling edge signal. Set To 0 by program to enable a low level signal on external interrupt1 to generate an interrupt 1IE0 External interrupt 0 Edge flag. Not related to timer operations 0 IT0 External interrupt 0 signal type control bit. Same as IT0.

 Serial Interface SI program classified  (1) SIMPLEX  (2) HALF DUPLEX SYNCHRONOUS SERIAL  (3) FULL DUPLEX ASYNCHRONOUS UART MODE  (1) SBUF (8 serial received bits or transmission bits register depending upon instruction is using SBUF as source or destination)  (2) (a) SCON (8-serial modes cum control bits register) (b) PCON both are SFR  The serial port of 8051 is full duplex it can transmit and receive simultaneously.  The register SBUF is used to hold the data. The special function register SBUF is physically two registers. One is, write-only and is used to hold data to be transmitted out of the 8051 via (a)TXD. The other is, read-only and holds the received data from external sources via (b)RXD.  Both mutually exclusive registers have the same address 099H.

SERIAL PORT CONTROL REGISTER (SCON)  Register SCON controls serial data communication. Address: 098H (Bit addressable)

SM2: multi processor communication bit REN: Receive enable bit TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received) RB8: Received bit 8 TI: Transmit interrupt flag RI: Receive interrupt flag Power Mode control Register (PCON) Register PCON controls processor power down, sleep modes and serial data band rate. Only one bit of PCON is used with respect to serial communication. The seventh bit (b7)(SMOD) is used to generate the baud rate of serial communication. Address: 87H SMOD: Serial baud rate modify bit GF1: General purpose user flag bit 1 GF0: General purpose user flag bit 0 PD: Power down bit IDL: Idle mode bit

Data Transmission Transmission of serial data begins at any time when data is written to SBUF. Pin P3.1 (Alternate function bit TXD) is used to transmit data to the serial data network. TI is set to 1 when data has been transmitted. This signifies that SBUF is empty so that another byte can be sent. Data Reception Reception of serial data begins if the receive enable bit is set to 1 for all modes. Pin P3.0 (Alternate function bit RXD) is used to receive data from the serial data network. Receive interrupt flag, RI, is set after the data has been received in all modes. The data gets stored in SBUF register from where it can be read. Serial Data Transmission Modes: Mode-0 In this mode, the serial port works like a shift register and the data Transmission works synchronously with a clock frequency of f osc /12. Serial data is received and transmitted through RXD. 8 bits are transmitted/ received at a time. Pin TXD outputs the shift clock pulses of frequency f osc /12, which is connected to the external circuitry for synchronization. The shift frequency or baud rate is always 1/12 of the oscillator frequency.

Mode-1 (standard UART mode) In mode-1, the serial port functions as a standard Universal Asynchronous Receiver Transmitter (UART) mode. 10 bits are transmitted through TXD or received through RXD. The 10 bits consist of one start bit (which is usually '0'), 8 data bits (LSB is sent first/received first), and a stop bit (which is usually '1'). Once received, the stop bit goes into RB8 in the special function register SCON. The baud rate is variable. The following figure shows the way the bits are transmitted/ received.

Bit time= 1/f baud In receiving mode, data bits are shifted into the receiver at the programmed baud rate. The data word (8-bits) will be loaded to SBUF if the following conditions are true. 1. RI must be zero. (i.e., the previously received byte has been cleared from SBUF) 2. Mode bit SM2 = 0 or stop bit = 1. After the data is received and the data byte has been loaded into SBUF, RI becomes one. Mode-1 baud rate generation Timer-1 is used to generate baud rate for mode-1 serial communication by using overflow flag of the timer to determine the baud frequency. Timer-1 is used in timer mode-2 as an auto-reload 8-bit timer. The data rate is generated by timer-1 using the following formula.

SMOD is the 7 th bit of PCON register f osc is the crystal oscillator frequency of the microcontroller It can be noted that f osc / (12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2, which is the auto-reload mode.If timer-1 is not run in mode-2, then the baud rate is, Timer-1 can be run using the internal clock, fosc/12 (timer mode) or from any external source via pin T1 (P3.5) (Counter mode).

 Interrupts are the events that temporarily suspend the main program, pass the control to the external sources and execute their task. It then passes the control to the main program where it had left off.  8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled or disabled by setting bits of the IE register and the whole interrupt system can be disabled by clearing the EA bit of the same register.  Microcontrollers Interrupts has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled or disabled by setting bits of the IE register and the whole interrupt system can be disabled by clearing the EA bit of the same register. Timer 0 overflow interrupt- TF0 Timer 1 overflow interrupt- TF1 External hardware interrupt- INT0 External hardware interrupt- INT1 Serial communication interrupt- RI/TI

THE SCHEMATIC REPRESENTATION OF THE INTERRUPTS IS AS FOLLOWS

IE (INTERRUPT ENABLE) REGISTER This register is responsible for enabling and disabling the interrupt. EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their meanings are shown in the following figure. EAIE.7It disables all interrupts. When EA = 0 no interrupt will be acknowledged and EA = 1 enables the interrupt individually. - IE.6 Reserved for future use. - IE.5 Reserved for future use. ESIE.4Enables/disables serial port interrupt. ET1IE.3Enables/disables timer1 overflow interrupt. EX1IE.2Enables/disables external interrupt1. ET0IE.1Enables/disables timer0 overflow interrupt. EX0IE.0Enables/disables external

 We can change the priority levels of the interrupts by changing the corresponding bit in the Interrupt Priority (IP) register as shown in the following figure. A low priority interrupt can only be interrupted by the high priority interrupt, but not interrupted by another low priority interrupt.  If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served.  If the requests of the same priority levels are received simultaneously, then the internal polling sequence determines which request is to be serviced.

Each interrupt source can be programmed to have one of the two priority levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt. If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served. If the requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced. Thus, within each priority level, there is a second priority level determined by the polling sequence, as follows.

EXTERNAL INTERRUPT INT0 & INT1 The external interrupts are the interrupts received from the (external) devices interfaced with the microcontroller. They are received at INT x pins of the controller. The 8051 has two external hardware interrupts PIN 12 (P3.2) and Pin 13 (P3.3) of the 8051, designated as INT0 and INT1 are used as external hardware interrupts. Upon activation of these pins, the 8051 gets interrupts in what ever it is doing and jumps to the vector table to perform the interrupt service routine. Type of Interrupt 1)Level-TriggereInterrupt 2)Edge-TriggeredInterrupt

TYPE OF INTERRUPT LEVEL-TRIGGERED INTERRUPT EDGE -TRIGGERED INTERRUPT  this mode, INT0 and INT1 are normally high and if the low level signal is applied to them  the microcontroller stops and jumps to the interrupt vector table to service that interrupt.  8051 makes INT0 and INT1 is when applied low l Level- Triggered Interrupt.  When Edge -Triggered Interrupt applied, we must program the bits of the TCON Register.  The TCON register holds among other bits and IT0 and IT1 flags bit the determine level- or edge triggered mode Of the hardware interrupt.

REGISTERS USED IN PROGRAMMING OF INT0 AND INT1 ARE TCON AND IE TCON

TR1=0 mean, to stop timer 1. TR1=1 mean, to start timer 1. TR0=0 mean, to start timer 0. TR0=1 mean, to start timer 0. TF1=1 mean overflow condition occur in Timer 1. TF1=0 mean Timer 1 is in running condition. TF0=1 mean overflow condition occur in Timer 0. TF0=0 mean Timer 0 is in running condition. IT1=1 mean interrupt trigger is negative edge sensitive. IT1=0 mean interrupt trigger is positive edge sensitive. IT0=1 mean interrupt trigger is negative edge sensitive. IT0=0 mean interrupt trigger is positive edge sensitive. IE1=1 mean interrupt enable Timer 1. IE1=0 mean interrupt enable Timer 1. IE0=1 mean interrupt enable Timer 0. IE0=0 mean interrupt enable Timer 0.

EA=1 enable this register’s use. EA=0 disable this register’s use. ES=1 enable serial interrupt. ES=0 disable serial interrupt. ET2=1 enable Timer 2 interrupt (8052 feature). ET2=0 disable Timer 2 interrupt (8052 feature). ET1=1 enable Timer 1 interrupt. ET1=0 disable Timer 1 interrupt. ET0=1 enable Timer 0 interrupt. ET0=0 disable Timer 0 interrupt. EX1=1 enable external/hardware interrupt(INT1). EX1=0 disable external/hardware interrupt(INT1). EX0=1 enable external/hardware interrupt(INT0). EX0=0 disable external/hardware interrupt(INT0).

Addressing Modes Instruction Register MOV A, B Direct MOV 30H,A Indirect ADD Immediate Constant ADD A,#80H Relative* SJMP AHEAD Absolute* AJMP BACK Long* LJMP FAR_AHEAD Indexed MOVC

1.Immediate addressing mode: Ex: MOV A,#6AH -> Where MOV stands for move, # represents immediate data.6AH is the data. It means the immediate date 6AH provided in instruction is moved into A register.

2.Register addressing mode: Here the operand in contained in the specific register of microcontroller. The user must provide the name of register from where the operand/data need to be fetched. The permitted registers are A, R7-R0 of each register bank. Ex: MOV A,R4-> content of R4 register is copied into Accumulator.

3. Direct addressing mode: In this mode the direct address of memory location is provided in instruction to fetch the operand. Only internal RAM and SFR's address can be used in this type of instruction. Ex: MOV A,#04H => Content of RAM address 04H is copied into Accumulator.

4. Register Indirect addressing mode: Here the address of memory location is indirectly provided by a register. The sign indicates that the register holds the address of memory location i.e. fetch the content of memory location whose address is provided in register. Ex: MOV => Copy the content of memory location whose address is given in R0 register.

5. Indexed Addressing mode: This addressing mode is basically used for accessing data from look up table. Here the address of memory is indexed i.e. added to form the actual address of memory. Ex: MOVC => here 'C' means Code. Here the content of A register is added with content of DPTR and the resultant is the address of memory location from where the data is copied to A register.

UIT 5 INSTRUCTION SET DATA TRANSFER INSTRUCTION ARITH MTIC AND LOGIC INSTRUCTION BOOLEAN VARIABLE MANIPULATION NSTRUCTIONS PROGRAME AND MACHINE CONTROLE INSTRUCTION SIMPLE PROGRAMES ADDITION SUBRACTION TWO 8 BIT 16 BIT MULTIPLICATION DIVISION LARGEST SMALAST SUM OF SERIES

8051 INSTRUCTIONS SET 8051 has about 111 instructions. These can be grouped into the following categories 1.Arithmetic Instructions 2.Logical Instructions 3.Data Transfer instructions 4.Boolean Variable Instructions 5.Program Branching Instructions The following nomenclatures for register, data, address and variables are used while write instructions. A: Accumulator B: "B" register C: Carry bit Rn: Register R0 - R7 of the currently selected register bank

Direct: 8-bit internal direct address for data. The data could be in lower 128bytes of RAM (00 - 7FH) or it could be in the special function register ( bit external or internal RAM address available in register R0 or R1. This is used for indirect addressing mode. #data8: Immediate 8-bit data available in the instruction. #data16: Immediate 16-bit data available in the instruction. Addr11: 11-bit destination address for short absolute jump. Used by instructions AJMP & ACALL. Jump range is 2 kbyte (one page). Addr16: 16-bit destination address for long call or long jump. Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all conditional jumps. bit: Directly addressed bit in internal RAM or SFR

ARITHMETIC INSTRUCTIONS MnemonicsDescriptionBytesInstruction Cycles ADD A, RnA A + Rn11 ADD A, directA A + (direct)21 ADD A ADD A, #dataA A + data21 ADDC A, RnA A + Rn + C11 ADDC A, directA A + (direct) + C21 ADDC A + C11 ADDC A, #dataA A + data + C21 DA ADecimal adjust accumulator 11 DIV ABDivide A by B A quotient B remainder 14

DEC AA A -111 DEC RNRN RN DEC DIRECT(DIRECT) (DIRECT) INC AA A+111 INC RNRN RN INC DIRECT(DIRECT) (DIRECT) INC DPTRDPTR DPTR +112 MUL ABMULTIPLY A BY B A LOW BYTE (A*B) B HIGH BYTE (A* B) 14 SUBB A, RNA A - RN - C11 SUBB A, DIRECTA A - (DIRECT) - C21 SUBB A - C11 SUBB A, #DATAA A - DATA - C21

LOGICAL INSTRUCTIONS MnemonicsDescriptionBytesInstruction Cycles ANL A, RnA A AND Rn11 ANL A, directA A AND (direct)21 ANL A ANL A, #dataA A AND data21 ANL direct, A(direct) (direct) AND A21 ANL direct, #data(direct) (direct) AND data32 CLR AA 00H11 CPL AAA11 ORL A, RnA A OR Rn11 ORL A, directA A OR (direct)11 ORL A ORL A, #dataA A OR data11 ORL direct, A(direct) (direct) OR A21 ORL direct, #data(direct) (direct) OR data32

RL ARotate accumulator left11 RLC ARotate accumulator left through carry 11 RR ARotate accumulator right11 RRC ARotate accumulator right through carry 11 SWAP ASwap nibbles within Acumulator 11 XRL A, RnA A EXOR Rn11 XRL A, directA A EXOR (direct)11 XRL A XRL A, #dataA A EXOR data11 XRL direct, A(direct) (direct) EXOR A21 XRL direct, #data(direct) (direct) EXOR data32

DATA TRANSFER INSTRUCTIONS MnemonicsDescriptionBytesInstruction Cycles MOV A, RnA Rn11 MOV A, directA (direct)21 MOV A, #dataA data21 MOV Rn, ARn A11 MOV Rn, directRn (direct)22 MOV Rn, #dataRn data21 MOV direct, A(direct) A21 MOV direct, Rn(direct) Rn22 MOV direct1, direct2(direct1) (direct2)32 MOV direct, #data(direct) #data32 A11 (direct)22

data21 MOV DPTR, #data16DPTR data1632 MOVC Code byte pointed by A + DPTR12 MOVC Code byte pointed by A + PC12 MOVC Code byte pointed by Ri 8-bit address)12 MOVX External data pointed by DPTR12 A (External data - 8bit address)12 A(External data - 16bit address)12 PUSH direct(SP) (direct)22 POP direct(direct) (SP)22 XCH RnExchange A with Rn11 XCH directExchange A with direct byte21 A with indirect RAM11 XCHD least significant nibble of A with that of indirect RAM11

BOOLEAN VARIABLE INSTRUCTIONS MnemonicsDescriptionBytesInstruction Cycles CLR CC-bit 011 CLR bitbit 021 SET CC 111 SET bitbit 121 CPL CC 11 CPL bitbit 21 ANL C, /bitC C. 21 ANL C, bitC C. bit21 ORL C, /bit C C + 21 ORL C, bitC C + bit21 MOV C, bitC bit21 MOV bit, Cbit C22

PROGRAM BRANCHING INSTRUCTIONS MnemonicsDescriptionBytesInstruction Cycles ACALL addr11PC + 2 (SP) ; addr 11 PC22 AJMP addr11Addr11 PC22 CJNE A, direct, relCompare with A, jump (PC + rel) if not equal 32 CJNE A, #data, relCompare with A, jump (PC + rel) if not equal 32 CJNE Rn, #data, relCompare with Rn, jump (PC + rel) if not equal 32 #data, relCompare A, jump (PC + rel) if not equal 32 DJNZ Rn, relDecrement Rn, jump if not zero22 DJNZ direct, relDecrement (direct), jump if not zero32 JC relJump (PC + rel) if C bit = 122 JNC relJump (PC + rel) if C bit = 022

JB bit, relJump (PC + rel) if bit = 132 JNB bit, relJump (PC + rel) if bit = 032 JBC bit, relJump (PC + rel) if bit = 132 PC12 JZ relIf A=0, jump to PC + rel22 JNZ relIf A ≠ 0, jump to PC + rel22 LCALL addr16PC + 3 (SP), addr16 PC32 LJMP addr 16Addr16 PC32 NOPNo operation11 RET(SP) PC12 RETI(SP) PC, Enable Interrupt12 SJMP relPC rel PC22 PC12 JZ relIf A = 0. jump PC+ rel22 JNZ relIf A ≠ 0, jump PC + rel22 NOPNo operation11