Chapter 2 – Transistors – Part 2 Field Effect Transistors (Unipolar Transistors) (Charge carriers: either electrons or holes)

Unipolar Transistors Bipolar Transistor

Bipolar Transistor Electrons and holes are crossing emitter junction

Field Effect transistor (FET) (or Unipolar transistors ) Field-effect transistors were invented by Julius Edgar Lilienfeld (Jewish Austro-Hungarian physicist) in 1925 and by Oskar Heil (German electrical engineer and inventor) in 1934. Practical devices were not able to be made until 1952 (the JFET). Commonly used for weak-signal amplification. Two types of FETs are : n-channel and p-channel FET.

The FET is a three terminal device i. e The FET is a three terminal device i.e. the source (S), drain (D), and gate (G). Source : Provides the source of charge carriers (electrons/holes) for the channel current ( equivalent to Emitter in Transistor). Drain : The place where the charge carriers are removed ( or “drained”) from the device ( equivalent to Collector in Transistor). . Gate : Controls the current flow in the channel ( equivalent to Base in Transistor).

9) In both n-channel and p-channel, the charge carriers always flow from the source connection to the drain connection. 10) In n-channel, charge carriers are electrons. 11) In p-channel, charge carriers are holes.

Current Controlled vs Voltage Controlled Devices Bipolar Transistor – Base current is nonzero. FET Transistor – No current is flowing in Gate circuit.

n-channel FET

FET Construction There are two types of JFET’s: n-channel and p-channel. The n-channel is more widely used. There are three terminals: Drain (D) and Source (S) are connected to n-channel Gate (G) is connected to the p-type material

p-channel FET

Major Application – Display Driving Circuit

FET – Fabrication and Operation (reverse- biased)

n-channel FET

N-Channel FET Operation The nonconductive depletion region becomes thicker with increased reverse bias. (Note: The two gate regions of each FET are connected to each other.)

Only one carrier type is involved in charge flow. The charge flow is due to drift (as diffusion current small). The voltage applied to the gate (reverse-biased) controls the current flowing in the source-drain channel. No current flows through the gate electrode. Thus the gate is essentially insulated from the source-drain channel.

6) Near the Drain end of the Gate : (i) Width of channel narrowest and (ii) junction width is widest. 7) Because here the reserve bias is the sum of Gate potential (Vgs) and the Drain potential (Vds). 8) Nonuniform voltage drop along the channel and nonlinear variation in channel width make the exact analysis complicated.

N-Channel JFET Symbol January 2004 ELEC 121

Saturation At the pinch-off point: • any further increase in VGS does not produce any increase in ID. VGS at pinch-off is denoted as Vp. • ID is at saturation or maximum. It is referred to as IDSS. • The ohmic value of the channel is at maximum.

ELEC 121

Drain Current , Id Pinch-off voltage is a 'Drain-Source' voltage after which the drain source current becomes almost constant (saturates) and at Vgs = 0V. pinch off = 핀치 끄기 Pinch = 핀치

For n-channel JFET Pich-off voltage is positive. But because Vgs(off) (the gate source voltage at which there is no drain-source current) voltage is negative and by accident equal to the magnitude of the pinch off voltage. Hence: |Vgs(off)| = |Vp| the magnitude of the pinch off voltage is equal to Vgs(off). And this is why we can say that |Vp| = |Vgs(off)| but in the same time Vp is a saturation voltage. But the only difference is the minus sign. Because Vgs(off) is negative but Vp is positive.

Expression for drain current in saturation region. Vgs > Vp and Vds = Vgs – Vp Drain current in the active region Vds ≥ Vgs - Vp

Drain current saturation occurs when the Vds equals the Vgs minus the Vp (pinch off voltage). The value of the saturated drain current, ID is then given by the above equation. active region /Channel off n-channel FET

ID  IDSS As VGS becomes more negative: • the JFET will pinch-off at a lower voltage (Vp). • ID decreases (ID < IDSS) even though VDS is increased. • Eventually ID will reach 0A. VGS at this point is called Vp or VGS(off). • Also note that at high levels of VDS the JFET reaches a breakdown situation. ID will increases uncontrollably if VDS > VDSmax.

FET as a Voltage-Controlled Resistor The region to the left of the pinch-off point is called the ohmic region. The JFET can be used as a variable resistor, where VGS controls the drain-source resistance (rd). As VGS becomes more negative, the resistance (rd) increases.

Transfer (Transconductance) Curve From this graph it is easy to determine the value of ID for a given value of VGS It is also possible to determine IDSS and VP by looking at the knee where VGS is 0

Exercise : 1 For n-channel FET Id = Idss (1 – Vgs / Vp )2, Vp = 3.0 V Find Id Vgs = -2 , -1, and 1V Vgs = 0 V If Id = 0 mA , Vgs = ?

N-channel FET – Biasing

The input impedance of the FET is extremely large (in the range of 1010–1015 Ω). With a positive voltage on the drain, with respect to the source, electron current flows from source to drain through the CHANNEL. If the gate is made negative with respect to the source, an electrostatic field is created, which squeezes the channel (i.e. channel width is reduced) and reduces the current. Signal voltages applied to the gate result in corresponding variations in drain current.

Another definition of pinch-off voltage The physical meaning of this term (Idss) leads to one definition of pinch-off voltage, VP , which is the value of Vds (drain-source voltage) at which the maximum Idss flows.

Current-voltage characteristics ( or collector characteristics) p-channel FET Current-voltage characteristics ( or collector characteristics) Vgs = - 0.5V Vgs = 0 V Vgs = 0.5V Vgs = 1.0 V Vds (V) Id (mA) ---- 5 10 15 20 Gate is reversed biased.

Operation : Current – voltage characteristics of p-channel FET

The Transfer Characteristics The transfer characteristic for a JFET can be determined experimentally, keep drain-source voltage, Vds constant, and determine drain current, Id for various values of gate-source voltage, Vgs.

For p-channel FET When Vgs= VP with Vds= 0 (we get using Vp = Vgs + Vds ), the two depletion layers touch over the entire channel length and the whole channel is closed.

Characteristcs shows the variation of Id with Vgs. Idss denote the drain current with shorted gate. The curve extends on both sides i.e. Vgs can be negative as well as positive. Since Vgs can be positive also Idss is not maximum value of drain current. Characteristics shows square law dependence (Id  V2gs). Transfer characteristics is an alternative way of describing the nonlinear electrical properties of the FET.

For n-channel FET