Sungho Kang Yonsei University Logic BIST Sungho Kang Yonsei University

Outline Introduction Basics Issues Weighted Random Pattern Generation BIST Architectures Deterministic BIST Conclusion

Test patterns are generated on-chip Built In Self Test Input Test patterns are generated on-chip Responses to the test patterns are also evaluated on chip External operations are required only to initialize the built-in tests and to check the test results (go/no-go) Pattern Generation (random pattern) Test/ BIST Controller MUX Normal Circuit under Test Output Response Monitor Output

Constraints of BIST Initial design investment Area overhead Pin overhead Performance overhead Fault coverage Aliasing problem

Test Pattern Generation Stored Pattern Exhaustive Pattern Pseudo Exhaustive Pattern Pseudo Random Pattern Weighted Random Pattern

Combinational Circuit Classification Partial Dependence Circuit (PDC) No output depends on all inputs Exhaustive test if possible Else output verification test Else segment verification Full Dependence Circuit (FDC) Some output depends on all inputs

PDC Example Example circuit Dependency matrix Dij = 1 if output I depends on input j ; otherwise Dij=0

PDC Example Reordering and grouping the inputs produce the following modified matrix

PDC Example In each group there must be less than two 1s in each row and the number of groups should be minimal This insures that no output is driven by more than one input from each group Finding such a partition is NP-complete ORing each row within a group to form a single column

PDC Example p=4 and w=3 odd parity A B C D 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 Pseudo exhaustive test set consists of 8 patterns instead of 128 Among 4 groups, 8 patterns using any 3 inputs are necessary

Segment Verification Segmentation testing via path sensitization Sensitized path is established from C to F Use 2n1+2n2 patterns instead of 2n1+n2 patterns

Linear Feedback Shift Register The state of shift register depends only on the prior state = 1 D Q c 2 1 n n-1 3 a -1 -2 -n+1 -n m m-1 m-2 m-n+1 m-n Next State Current State

Linear Feedback Shift Register Pseudo Random Pattern Generation Characteristic Polynomial : 1+x2+x3 Initial condition (1,0,0) : x Q1 : x / (1+x2+x3) Q2 : x2 / (1+x2+x3) Q3 : x3 / (1+x2+x3)

LFSR : 1+x2+x3 When initial state is 100 Q1 Q2 Q3 1 0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1

Linear Feedback Shift Register When initial state is 000 Q1 Q2 Q3 0 0 0

Weighed Random Patterns All patterns not equally likely Pseudo random test patterns are inefficient when random-pattern-resistant faults exist. Make Prob[1]  Prob[0] at pattern sources Random resistant faults Consider a 32 input AND and output s-a-1 fault The output s-a-0 is detected when all inputs are 1 When pseudo random testing is used, the detection probability is 1/232

Weight Generation Methods Structural analysis Small number of patterns and weight sets Easy implementation Poor fault coverage Deterministic test sets All non-redundant faults can be detected A high number of random patterns and weights Large hardware overhead Combined both methods

Multiple Weight Sets Consider AND output s-a-1 and OR output s-a-0 If the same weights are applied, one of two faults are hard to detect. Necessary to have 2 different weight sets (1/232, 1-1/ 232) (1-1/ 232, 1/ 232) The efficiency of multiple weight set is determined by both the number of weight sets (r), and the total number of random test patterns to be applied (N). The goal of weight generation is to reduce both r and N AND OR I1 I2 I3 I4

Multiple Weight Sets Single weight set Advantage Small hardware overhead Disadvantages Low fault coverage Long test pattern length Multiple weight sets Advantages High fault coverage Short test pattern length Large hardware overhead

Response Analysis Signature : output of the compactor Aliasing A faulty circuit produces a signature that is identical to the signature of a fault free circuit

Signature Analysis Initial Value : 000 Good Good Faulty Faulty Patterns Responses Patterns Responses Z1 Z2 Z3 Q1 Q2 Q3 Z1 Z2 Z3 Q1 Q2 Q3 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1

Aliasing Initial Value : 000 Good Good Faulty Faulty Patterns Responses Patterns Responses Z1 Z2 Z3 Q1 Q2 Q3 Z1 Z2 Z3 Q1 Q2 Q3 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 1

MISR Normally, a single input signature analyzer is not used due to testing overhead Aliasing Probability : 1/2n All error patterns are equally likely

Test-per-Clock Test patterns are applied to CUT every clock cycle Additional logic and delay are required between the input FF and CUT BILBO like type: Cannot perform compression and pattern generation concurrently Entire test is scheduled and divided into sessions Complex test control unit is required

Test-per-Scan LFSR is used to serially shift in a sequence of bits into the scan chain No additional logic is inserted between the scan FF and CUT Testing time is increased considerably for long scan chain STUMP like type : Control unit does not need to distinguish between different test sessions It must count the patterns and bits

STUMPS Self Testing Using MISR and Parallel SRSG Centralized and separate BIST Multiple scan paths Reduction in test time Lower overhead than BILBO but takes longer to apply

BILBO(Built-In Logic Block Observer) B1 B2 Mode 1 1 Normal Mode 0 1 Reset 0 0 Shift Register 1 0 Signature Analyzer

BILBO To test A To test B R1 : RPG R2 : Signature Analyzer R2 : RPG Architectures To test A R1 : RPG R2 : Signature Analyzer To test B R2 : RPG R1 : Signature Analyzer

Test Schedule Test session Architectures Test session An assignment of test modes to BILBO registers to test one or more blocks Test scheduling problem Determine the minimal number of test sessions required to test all blocks of combinational logic Determine the minimal colors that can be assigned to the nodes of a graph such that no edge connects two nodes of the same color More complex when the test time for each block is considered

Phase Shift BIST

Multiple Seed LFSR LFSR v CUT BIST Controller MISR Method of Encoding deterministic pattern to each seed Each seed is an encoded deterministic pattern Long LFSRs may be required for circuits with a large number of specified bits in each pattern Methods of Calculating BIST Seeds Using hard fault identification and ordering Deterministic test cube compression : Iterative merging compatible cubes Fast simulation based procedure LFSR CUT MISR Seed0 Seed1 Seed2 BIST Controller Seed ROM Test clock v

Non-LFSR PRPG CUT ROM Johnson counter(Twisted-Ring Counter) TRC is designed by adding a MUX and an inverter to the serial input of the scan register If TRC’s length n is a power of 2, then for any initial state, the TRC will always cycle through 2n distinct states To generate various patterns, reseeding method is adopted Can apply both test-per-clock and scan-BIST architectures ROM 00 10 4-1 11 MUX Input scan register Log2n bit binary counter SCAN enable CUT Response analyzer 2bit Enable k 1

Bit Fixing/Bit Flipping Most of these methods are applied to test-per-scan architecture Bit fixing experiment results High fault coverage with practical test application time Since the number of bits required to be fixed is often high, the combinational logic overhead required may be substantial Bit flipping experiment results Mapping logic generally requires lower overhead Overall pattern generation overhead can still be high because of the large external LFSR Sequential CUT t0 t1 … ... tL-1 s0 s1 sn-1 Scan chain Bit Flipping Circuit Signature Analyzer

Embedding Deterministic Patterns Only scan-BIST Modify the random sequence at a few bit positions Complete fault coverage Generated patterns depends on the state of the test control unit LFSR can be very small Area overhead is smaller than that of the 32-bit LFSR for ISCAS85 and ISCAS89 benchmark circuits Automatic synthesis procedure is possible BIST Control Sequential CUT Short LFSR s0 s1 … ... sn-1 Scan chain Sequence Modifying Circuit Signature Analyzer p0 p1 b0 b1 Pattern counter Bit counter

BIST Using Core Functions Hardware overhead low and no performance degrading Processor emulates an LFSR base pseudo random test first, and after that it emulates the reseeding scheme Most of accumulator based pattern generation by simple adders, subtractors, or MAC circuits All of them generate pseudo random, or pseudo exhaustive patterns with a similar quality as LFSRs do Only one accumulator based deterministic BIST In adder based accumulator based structure, deterministic pattern generated by reseeding scheme Test response compaction Aliasing probabilities same as that of LFSR based signature analysis Method of core functions randomizing

LT-RTPG Low transition Possible decrease in fault coverage due to low toggle probability Use non-adjacent inputs for neighboring positions on the scan chain No decrease in fault coverage Good for a circuit with a large number of primary and state inputs LFSR T FF … k r LT-RTPG Scan Chain CUT m Sin Sout

BIST Issues Test point insertion is necessary for many circuits Suppressing X generators Non-scan FF, Memory, Combinational loop, Undriven PIs, Bus contention, Violation on a wire gate Bounding X generators and making detour through space compactors On-line BIST for intermittent faults and transient faults Two-pattern generator and compactor for delay faults Hardware sharing between MBIST and LBIST Multiphase-clock, multi-clock generation Design specific BIST Pattern generator compatible with both test-per-clock and test-per-scan architecture BIST supporting partial scanned circuits

Conclusion In BIST, the test pattern generation and the output response evaluation are done on chip Requirements of a BIST scheme Easy implementation Small area overhead High fault coverage