Advancement on the Analysis and Mitigation of 11th APRIL 2018 SpacE FPGA Users Workshop - SEFUW Advancement on the Analysis and Mitigation of SETs on Flash-based FPGAs Sarah Azimi1 Boyang Du1 Luca Sterpone1 David Merodio Codinachs2 Politecnico di Torino- CAD Group1 Dipartimento di Automatica e Informatica Torino- Italy European Space Agency2 The Netherlands

Motivations Space environment is characterized by several types of radiation particles: Heavy Ions Protons Neutrons Single Event Transient Effect Total Ionizing Dose Effect Single Event Latch-up Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Radiation effects on Flash-based technology Motivations Radiation effects on Flash-based technology ProASIC3 RTG4 Examples of transient pulses generated by particle incident Flash-based FPGA Versatile of ProASIC3 Logic Element of RTG4 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Current pulse generates a Single Event Transient - SET Motivations Current pulse generates a Single Event Transient - SET SET may propagate through multiple circuit paths Generation of Multiple SEUs on registers SET generation SET propagation Multiple SEUs Computational Register (operand) Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands SET Characterization Focus of SET Characterization Analysis of SET propagation through Next combinational logics Routing resources Fan-out gate load Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands SET Generation Main methods to emulate SET pulses induced by particles striking the semiconductor of the devices: Radiation Test Laser Test In-Circuit Test Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands In-Circuit Test In-Circuit test generated pulse depends on: Routing delay Inverters Propagation time Signal Generator Routing Delay Routing Delay IN (SET Source) IN (SET Source) Routing Delay INVs Propagation Delay Signal Generator Pulse Pulse Width Pulse Width = ∆INV - ∆Routing Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Global developed methodology for SET characterization Circuit under the test considering four different scenarios Path of Gates Path of Gates with Fanout Divergence Paths Convergence Paths In-Circuit Test Circuit Under the Test External SET measurement Pulse Generator Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 1 – Path of Gates Characterization of logical gates Using several lengths of Inverter-string Injecting SET at the input of the strings Measuring SET at the end of the strings Internal Injector Inverter-String Signal Generator Output SET Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 1 – Path of Gates Characterization of logical gates Placed side by side Minimal distance between each versatile Internal Injector Inverter String Microsemi Libero SoC 11.7 Commercial Design Tool Environment Placement Microsemi Libero SoC 11.7 Commercial Design Tool Environment Routing Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 1 – Path of Gates Characterization of logical gates Four string with 40,60,80 and 100 Inverter gates By increasing string length, PIPB increases By increasing string length, delay increases INVs [#] Source SET [ns] Output SET [ns] PIPB Delay [ns] 40 7.2 1 6.8 60 8 1.11 10.2 80 10 1.25 18.4 100 7.4 8.8 1.18 30.4 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 2 – Inverter Path with Fanout Characterization of gates chain including various fanout Connecting fanout of inverters to the beginning of the string Minimal distance connection between each versatile Internal Injector Inverter-String Signal Generator Output SET Fanout Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 2 – Inverter Path with Fanout Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 100 Inverters as string Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 2 – Inverter Path with Fanout Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 40, 60, 80 and 100 Inverters as string Chain 40 Chain 60 Chain 80 Chain 100 PIPB Delay [ns] Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 2 – Inverter Path with Fanout Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 40, 60, 80 and 100 Inverters as string Increasing PIPB by increasing the length of string Attenuating of PIPB by increasing fanout Chain 40 Chain 60 Chain 80 Chain 100 PIPB Delay [ns] Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

By Increasing the fanout, the delay of the circuit is not changing Scenario 2 – Inverter Path with Fanout Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 40, 60, 80 and 100 Inverters as string Increasing PIPB by increasing the length of string Attenuating of PIPB by increasing fanout By Increasing the fanout, the delay of the circuit is not changing Chain 40 Chain 60 Chain 80 Chain 100 PIPB Delay [ns] Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 3 – Divergence Paths Characterization of SET while there is an occurrence of divergence of combinational paths Propagation of SET through multiple paths Divergence Point Path (A) SET (A) SET (B) Path (B) Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 3 – Divergence Paths Characterization of SET while there is an occurrence of divergence of combinational paths Adding second inverter string in the middle of the main string Observing SET at the end of both strings Internal Injector Main Inverter-String Signal Generator Divergence Point Output SET (main) Output SET (Secondary) Secondary Inverter-String Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 3 – Divergence Paths Characterization of SET while there is an occurrence of divergence of combinational paths 100 Inverter gates as main string 60, 80 and 100 Inverter gates as secondary string PIPB-main PIPB-Secondary PIPB Delay [ns] Number of INVs in the secondary string Number of INVs in the secondary string Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 4 – Convergence Paths Characterization of SET while traversing through divergence point and uniting at convergence point Divergence Point Path (A) Convergence Point Path (B) Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 4 – Convergence Paths Overlapping SET outcome at the convergence point Minimal difference on the propagation delay of two paths, SET with Extremely large width Time [ns] Voltage [v] Overlapped C-SET Large difference on the propagation delay of two paths, SET shapes are provided as two separate pulses Time [ns] Voltage [v] SET (A) SET (B) Delay (A) - Delay (B) Divergence Point Delay (A) Convergence Point Delay (B) Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 4 – Convergence Paths Characterization of SET while traversing through divergence point A, propagate through different logical paths B, C and routings and reaching to the convergence point D. Internal Injector Main Inverter-String Signal Generator A Path (B) D Output SET (main) Path (C) Routing Delay Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Scenario 4 – Convergence Paths SET outcome at the convergence point SET Guard Gate Filtering Delay (C) – Delay (B) Case (III) Delay (C) – Delay (B) Case (II) Delay (C) – Delay (B) Case (I) Max SET Width Delta Delay Case (III) Case (II) Case (I) Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands SETA Tool SETA: a CAD tool to evaluate the sensitivity of the implemented circuit regarding SET targeting SET propagation PIPB effect Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Convergence SET analyzer C-SETA Tool C-SETA: a CAD tool to evaluate the sensitivity of the implemented circuit regarding Convergence-SET Microsemi Libero SoC Microsemi Libero SoC .pdc .sdf .v HDL Synthesized netlist Convergence SET analyzer (C-SETA) C-SET Error Occurrence Mapping Place and Route Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

C-SETA on Real Scenarios Analyzing the circuits SET sensitivity using SETA and C-SETA implemented on A3P250 Flash based FPGA Injecting SETs lower than 1 ns Characteristics of the Benchmark Circuits Circuits Versatile [#] FFs [#] Frequency [MHz] B05 415 66 47 B09 493 67 46 B12 565 123 48 B13 162 50 52 CORDIC 956 240 45 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

C-SETA on Real Scenarios Analyzing the circuits SET sensitivity using SETA and C-SETA Implemented on A3P250 Flash based FPGA Injecting SETs lower than 1 ns Comprehensive SET Sensitivity Using SETA and C-SETA Tool Circuits Totally Filtered [#] Partially Filtered [#] Broadened [#] Possible C-SET [#event] B05 46 9 8 423 B09 47 3 11 29 B12 102 1 13 1665 B13 21 14 7 44 CORDIC 161 12 39 318 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands Future Advancements Execution of radiation test for experimental validation of C-SET Application of C-SET technique to RTG4 family C-SET software delivery Supported by ESA under contract: SEE analysis and mitigation on SRAM and Flash-based FPGAs Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands

Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands Thank You! sarah.azimi@polito.it boyang.du@polito.it luca.sterpone@polito.it david.merodio.codinachs@esa.int Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands