Electronics for Physicists Lecture 14 Sequential Logic

Electronics for physicists Logic with feed-back Feed-back in digital circuits can: store state lead to unable states November 2018 Electronics for physicists

Electronics for physicists Sequential logic Sequential logic is the combination of combinational logic with memory. The output state depends on the current input states and on previous input or output states. Simple sequential logic devices flip-flop counter shift register Complex sequential logic devices Finite state machines (FSM) November 2018 Electronics for physicists

RS flip-flop 2 inputs, 2 outputs truth table for RS flip-flop 2 inputs, 2 outputs Labeling of 𝑅 and 𝑆 is irritating, but useful. R = reset: R = 1 ( R = 0)  Q = 1 S = set: S = 1 ( S = 0)  Q = 0 R = S = 1 ( R = S = 0) is forbidden state. Transition to R = S = 1 preserves previous state. November 2018 Electronics for physicists

Electronics for physicists RS flip-flop Why is R = S = 1 and 𝑄 = Q forbidden? R = S = 1 makes no sense. (Why set and reset at the same time?) (Don´t brake and accelerate your car simultaneously while driving!) 𝑄 = 1 and Q = 1 are not orthogonal. When moving from R = S = 1 to R = S = 0, result is unpredictable could be either of 𝑄 = 1, Q = 0 or 𝑄 = 0, Q = 1 November 2018 Electronics for physicists

Electronics for physicists Clocked RS flip-flop truth table for clocked RS flip-flop. x = any state clocked RS flip-flop one additional input C (clock) If C = “0”, previous state is maintained, otherwise identical to non-clocked RS flip-flop. (Recall NAND ≙ 0  1 gate) What is the clock good for ? Why is most digital electronics clocked? November 2018 Electronics for physicists

Bistable Multivibrator This is a simple latch and memory cell. Note the cross-coupled transistors Note the hierarchy of resistor values R = S = 1 is not well-defined November 2018 Electronics for physicists

D flip-flop From RS flip-flop to D flip-flop Forbidden state is eliminated ! November 2018 Electronics for physicists

D flip-flop clocked D flip-flop truth table for clocked D flip-flop. x = any state circuit symbol of clocked D flip-flop November 2018 Electronics for physicists

Edge-triggered D flip-flop input and output states of triggered D flip-flop as a function of time Master Slave QM Qs circuit symbol triggered D flip-flop Output QS changes during clock transition from C = “0”  “1” only. Why is this so ? November 2018 Electronics for physicists

Electronics for physicists Shift register A shift register is a chain of transparent flip-flops, sharing the same clock. The output of flip-flop (i) is transferred to the input of the next flip-flop (i+1) and stored. Why is data to input flip-flop not instantly shifted to output flip-flop ? November 2018 Electronics for physicists

Shift register Example: data sequence “1101” LSB first, MSB last! The initial state of the shift register be “0000” . 4 clock cycles are needed to transfer the bit sequence into the SR flip-flops 1 to 4. Shift register truth table November 2018 Electronics for physicists

Trigger basics (ATLAS) Lot’s of data!! Raw data before L1 trigger: ~10 Pbyte/sec LEVEL 1 Input rate: ~ 1 GHz (40 MHz x 25 events) Accept rate: 75 KHz  130 Gbyte/sec Processing time: ~2 µsec; Latency: 2.5 µsec Technologies: Electronics/Firmware LEVEL 2 Accept rate: 2 KHz  1.3 Gbyte/sec Processing Time: ~40 ms  Region of Interests Technologies: Firmware, Software/Networks Event Filter Accept Rate: 200 Hz  up to 400 Mbyte/sec Processing Time: ~4 sec Technologies: Software/Networks L1 L2 L3 November 2018 Electronics for physicists

Digital pipelines at LHC Raw data volume of the ATLAS SCT is Pb/s (≈ 6M ch. x 40 MHz x a few bits/ch.) Zero-suppression and data compression schemes reduce this by a factor of ≈ 100 A 132-cell pipeline provides 132 x 25 ns = 3.3 μs of latency for the L1 trigger decision Note the second pipeline, the derandomizing buffer (3 x 8 events deep) November 2018 Electronics for physicists

Electronics for physicists Toggle flip-flop T = “1” corresponds to circuit on the left. For T = “0”, D is connected internally to Q. Toggle flip-flop acts as a frequency divider November 2018 Electronics for physicists

Pattern recognition with a SR This circuit recognizes the bit sequence “1101” in an arbitrary string of data. Note that this requires to access each FF in parallel. November 2018 Electronics for physicists

Electronics for physicists Ring counter Initializing the FFs with “1000”, the counter counts through the states: “1000”, “0100”, “0010”, “0001” and then starts again… Can we do better than 4 states with four FFs ? November 2018 Electronics for physicists

Electronics for physicists Johnson counter What is different from the simple ring counter ? When initializing the FFs with “1000”, the Johnson counter produces 8 states. November 2018 Electronics for physicists

State diagram of a 2-bit SR We have 4 states (Z1 – Z3) corresponding to the content of the SR Depending on the value of the new bit (nb) to move into the SR, the state Z is changed or not. We introduce the variables A1A0 to indicate the old content of the SR, N1N0 to indicate the new content, and the output variables Q1Q0 (with Q1Q0 = A1A0) . November 2018 Electronics for physicists

From state diagram, to state table, to state equation nb A1 A0 To reconstruct N0 from A0, A1 and nb, use sum of products November 2018 Electronics for physicists

Electronics for physicists Pattern recognition Recognize pattern “101” FIFO – first in, first out Trigger pattern: 1 # of hits x Actual patterns: 2 3 November 2018 Electronics for physicists

Patter recognition of “101” with a SR We have 4 states (Z1 – Z3) depending on the number of matching bits in the SR The output variable Q0 indicates if a pattern matches (Q0 = “1”) or not (Q0 = “0”). November 2018 Electronics for physicists

State table and equation # of hits: decimal and binary November 2018 Electronics for physicists

From state diagram, to state table, to state equation November 2018 Electronics for physicists