Approximate Quaternary Addition with the Fast Carry Chains of FPGAs

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Presentation transcript:

Approximate Quaternary Addition with the Fast Carry Chains of FPGAs Sina Boroumand1, Hadi P. Afshar, Philip Brisk2 1University of Tehran, IR 2University of California, Riverside, US

Approximate Quaternary Adder This paper presents a synthesis and mapping technique that allows to add 4 numbers (rather than 3) using the fast carry chains of FPGAs. The adder would be approximate and can be exploited to build inexact multipliers. The approximate multipliers built by the proposed adder would be faster and smaller. Given an FPGA with a limited number of logic blocks, we would be able to fit more multipliers. The user can explore the adder tree design space to trade-off accuracy for reduced critical path delay and area. 21 March 2018 Approximate Quaternary Addition with the Fast Carry Chains of FPGAs