Word Assembly from Narrow Chips

Slides:



Advertisements
Similar presentations
Chapter 5 Internal Memory
Advertisements

55:035 Computer Architecture and Organization Lecture 7 155:035 Computer Architecture and Organization.
1 DIGITAL DESIGN I DR. M. MAROUF MEMORY Read-only memories Static read/write memories Dynamic read/write memories Author: John Wakerly (CHAPTER 10.1 to.
MEMORY ORGANIZATION Memory Hierarchy Main Memory Auxiliary Memory
1 Lecture 16B Memories. 2 Memories in General Computers have mostly RAM ROM (or equivalent) needed to boot ROM is in same class as Programmable Logic.
1 Pertemuan 17 Internal Memory: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1.
1 COMP 206: Computer Architecture and Implementation Montek Singh Wed., Nov. 13, 2002 Topic: Main Memory (DRAM) Organization.
Registers  Flip-flops are available in a variety of configurations. A simple one with two independent D flip-flops with clear and preset signals is illustrated.
Caching I Andreas Klappenecker CPSC321 Computer Architecture.
Chapter 5 Internal Memory
Memory Devices Wen-Hung Liao, Ph.D..
1 Lecture 16B Memories. 2 Memories in General RAM - the predominant memory ROM (or equivalent) needed to boot ROM is in same class as Programmable Logic.
1 EE365 Read-only memories Static read/write memories Dynamic read/write memories.
8-5 DRAM ICs High storage capacity Low cost Dominate high-capacity memory application Need “refresh” (main difference between DRAM and SRAM) -- dynamic.
Basic Computer Organization CH-4 Richard Gomez 6/14/01 Computer Science Quote: John Von Neumann If people do not believe that mathematics is simple, it.
Overview Booth’s Algorithm revisited Computer Internal Memory Cache memory.
1 The 8051 Microcontroller and Embedded Systems CHAPTER INTERFACING TO EXTERNAL MEMORY.
Chapter 4 ระบบหน่วยความจำ The Memory System
C.S. Choy95 COMPUTER ORGANIZATION Logic Design Skill to design digital components JAVA Language Skill to program a computer Computer Organization Skill.
ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.
1 CSCI 2510 Computer Organization Memory System I Organization.
Memory Systems Embedded Systems Design and Implementation Witawas Srisa-an.
Lecture 19 Today’s topics Types of memory Memory hierarchy.
CS 312 Computer Architecture Memory Basics Department of Computer Science Southern Illinois University Edwardsville Summer, 2015 Dr. Hiroshi Fujinoki
Wnopp Memory device Introduction n Memory Cell n Memory Word n Byte n Capacity n Address n Read Operation n Write Operation n Access Time n Volatile.
5-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL
1 load [2], [9] Transfer contents of memory location 9 to memory location 2. Illegal instruction.
CMSC 611: Advanced Computer Architecture Memory & Virtual Memory Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material.
Index What is an Interface Pins of 8085 used in Interfacing Memory – Microprocessor Interface I/O – Microprocessor Interface Basic RAM Cells Stack Memory.
Primary Storage The Triplets – ROM & RAM & Cache.
Chapter 5 - Internal Memory 5.1 Semiconductor Main Memory 5.2 Error Correction 5.3 Advanced DRAM Organization.
Appendix B The Basics of Logic Design
CMSC 611: Advanced Computer Architecture
Chapter 5 Internal Memory
William Stallings Computer Organization and Architecture 7th Edition
Homework Reading Tokheim, Chapter 12-1 through 12-4.
7-5 DRAM ICs High storage capacity Low cost
Digital Logic & Design Dr. Waseem Ikram Lecture 39.
Reducing Hit Time Small and simple caches Way prediction Trace caches
Dr. Rabie A. Ramadan Al-Azhar University Lecture 5
CS-301 Introduction to Computing Lecture 17
William Stallings Computer Organization and Architecture 7th Edition
The Triplets – ROM & RAM & Cache
William Stallings Computer Organization and Architecture 8th Edition
Lecture: DRAM Main Memory
William Stallings Computer Organization and Architecture 7th Edition
Introduction to Computing
Lecture: DRAM Main Memory
Universal Test Interface for Embedded DRAM Testing
William Stallings Computer Organization and Architecture 8th Edition
Morgan Kaufmann Publishers Computer Organization and Assembly Language
Digital Logic & Design Dr. Waseem Ikram Lecture 40.
Discovering Computers 2014: Chapter6
MICROPROCESSOR MEMORY ORGANIZATION
Computer System Design (Processor Design)
CMSC 611: Advanced Computer Architecture
Miss Rate versus Block Size
If a DRAM has 512 rows and its refresh time is 9ms, what should be the frequency of row refresh operation on the average?
Computer System Design Lecture 9
Chapter 4 Introduction to Computer Organization
UNIT-III Pin Diagram Of 8086
Chapter 5 Computer Organization
William Stallings Computer Organization and Architecture 8th Edition
Modified from notes by Saeid Nooshabadi
Bob Reese Micro II ECE, MSU
Cache Memory and Performance
Cache Memory and Performance
Lecture 2 (Memory) Computer Organization and Assembly Language. (CSC-210) Dr. Mohammad Ammad uddin.
Presentation transcript:

Word Assembly from Narrow Chips t A d d r e s s R / W C S C S C S R / W R / W . . . R / W A d d r e s s A d d r e s s A d d r e s s D a t a D a t a D a t a s s s p ´ s P chips expand word size from s bits to p x s bits.

CS501 Advanced Computer Architecture Lecture 38 Dr.Noor Muhammad Sheikh

Review

Cost of pins on a chip encourages narrow words for high capacity memory. Adding a data pin to a chip increases the number of bits it can store.

Read only Memory

Memory Hierarchy

Cache Memory

Memory Module

More chip capacity can be accommodated with fewer pins by increasing the address size rather than the word size.

Example Consider 4 chips with s=4, word size = 4bits Data bus = 16bits, o/p = 16 bits With SRAM chip no refresh required. With DRAM chip, RAS and CAS coordination.

Increasing the Number of Words by a Factor of 2k

Figure 7.19 (jordan)

Chip Matrix Using Two Chip Selects address m+q+k Horizontal decoder k m R/W cs1 cs2 address q A R/W Data Vertical decoder s One of 2m+q+k S-bit words

A Memory Module and Its Interface Address k+m Address register k m Chip/board selection Module select Memory boards and/or chip Control Signal generator Read Write Ready w Data register Data w

Dynamic RAM Module with Refresh Control k + m R a W i y D w / 2 f h n q G g C p b x B S

Two Kinds of Memory Module Organizations j k M o d u l e s b m A r + = - i t a c 1 2 – ( ) C n v w g h . .

A 2-D CMOS ROM Chip + v Address Row decoder CS 1 1

The cache mapping function CPU Word cache Main Memory Block address Mapping function

Cache operation are transport to the running program. The program issues effective addresses and read or write requests, and these requests are satisfied by memory Whether it is the cache or main memory that satisfies the request is unknown to the program The cache blocks are sometimes referred to as cache lines

Continued Cache mapping is responsible for all the cache operations. Cache is implemented in hardware to achieve high speed operation.

Mapping function determines the following: Placement strategies Replacement strategies Read and write policies