Discussion D5.1 Section Sections 13-3, 13-4

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Presentation transcript:

Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4 Basic Logic Gates Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

NOT Gate -- Inverter X Y 1 1

NOT Y = ~X (Verilog) Y = !X (ABEL) Y = not X (VHDL) Y = X’ Y = X Y = X (textook) not(Y,X) (Verilog)

NOT X ~X ~~X = X X ~X ~~X 0 1 0 1 0 1

AND Gate AND X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Z Y Z = X & Y

AND X & Y (Verilog and ABEL) X and Y (VHDL) X Y X * Y XY (textbook) and(Z,X,Y) (Verilog) V U

OR Gate OR X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 X Z Y Z = X | Y

OR X | Y (Verilog) X # Y (ABEL) X or Y (VHDL) X + Y (textbook) X V Y X U Y or(Z,X,Y) (Verilog)

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

NAND Gate NAND X Y Z 0 0 1 0 1 1 X 1 0 1 1 1 0 Z Y Z = ~(X & Y) 0 0 1 0 1 1 1 0 1 1 1 0 X Z Y Z = ~(X & Y) nand(Z,X,Y)

NAND Gate NOT-AND X Y W Z 0 0 0 1 0 1 0 1 X 1 0 0 1 1 1 1 0 W Z Y 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 X W Z Y W = X & Y Z = ~W = ~(X & Y)

NOR Gate NOR X Y Z 0 0 1 0 1 0 X 1 0 0 Z 1 1 0 Y Z = ~(X | Y) 0 0 1 0 1 0 1 0 0 1 1 0 X Z Y Z = ~(X | Y) nor(Z,X,Y)

NOR Gate NOT-OR X Y W Z 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 X W Z Y 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 X W Z Y W = X | Y Z = ~W = ~(X | Y)

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

NAND Gate X X Z Z = Y Y Z = ~(X & Y) Z = ~X | ~Y X Y W Z 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0

De Morgan’s Theorem-1 ~(X & Y) = ~X | ~Y Change & to | and | to & NOT all variables Change & to | and | to & NOT the result

NOR Gate X X Z Z Y Y Z = ~(X | Y) Z = ~X & ~Y X Y Z X Y ~X ~Y Z 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0

De Morgan’s Theorem-2 ~(X | Y) = ~X & ~Y Change & to | and | to & NOT all variables Change & to | and | to & NOT the result

De Morgan’s Theorem NOT all variables Change & to | and | to & NOT the result -------------------------------------------- ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y) ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y ~X & !Y = ~(~~X | ~~Y) = ~(X | Y) ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

Exclusive-OR Gate XOR X Y Z X Z 0 0 0 Y 0 1 1 1 0 1 1 1 0 Z = X ^ Y 0 0 0 Y 0 1 1 Z = X ^ Y xor(Z,X,Y) 1 0 1 1 1 0

XOR X ^ Y (Verilog) X $ Y (ABEL) X @ Y xor(Z,X,Y) (Verilog)

Exclusive-NOR Gate XNOR X Y Z X Z 0 0 1 Y 0 1 0 1 0 0 1 1 1 Z = X ~^ Y 0 0 1 Y 0 1 0 Z = ~(X ^ Y) Z = X ~^ Y xnor(Z,X,Y) 1 0 0 1 1 1

XNOR X ~^ Y (Verilog) !(X $ Y) (ABEL) X @ Y xnor(Z,X,Y) (Verilog)

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

Multiple-input Gates Z Z 1 2 Z Z 3 4

Multiple-input AND Gate Z 1 Output is HIGH only if all inputs are HIGH Z 1 An open input will float HIGH

Multiple-input OR Gate Z 2 Output is LOW only if all inputs are LOW Z 2

Multiple-input NAND Gate Z 3 Output is LOW only if all inputs are HIGH Z 3

Multiple-input NOR Gate Z 4 Output is HIGH only if all inputs are LOW Z 4