Reading: Study Chapter (including Booth coding)

Slides:



Advertisements
Similar presentations
Multiplication and Division
Advertisements

Datorteknik IntegerMulDiv bild 1 MIPS mul/div instructions Multiply: mult $2,$3Hi, Lo = $2 x $3;64-bit signed product Multiply unsigned: multu$2,$3Hi,
CMPE 325 Computer Architecture II
Cosc 2150: Computer Organization Chapter 9, Part 2 Integer multiplication and division.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Computer Organization Lecture 8 - Multiplication.
Integer division Pencil and paper binary division (dividend)(divisor) 1000.
THE ARITHMETIC-LOGIC UNIT. BINARY HALF-ADDER BINARY HALF-ADDER condt Half adder InputOutput XYSC
Division CPSC 321 Computer Architecture Andreas Klappenecker.
Henry Hexmoor1 Chapter 5 Arithmetic Functions Arithmetic functions –Operate on binary vectors –Use the same subfunction in each bit position Can design.
Chapter 6 Arithmetic. Addition Carry in Carry out
L10 – Multiplication Division 1 Comp 411 – Fall /19/2009 Binary Multipliers ×
Computer Organization Multiplication and Division Feb 2005 Reading: Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann.
Chap 3.3~3.5 Construction an Arithmetic Logic Unit (ALU) Jen-Chang Liu, Spring 2006.
DIGITAL SYSTEMS TCE1111 Representation and Arithmetic Operations with Signed Numbers Week 6 and 7 (Lecture 1 of 2)
1 Lecture 4: Arithmetic for Computers (Part 4) CS 447 Jason Bakos.
Chapter 5 Arithmetic Logic Functions. Page 2 This Chapter..  We will be looking at multi-valued arithmetic and logic functions  Bitwise AND, OR, EXOR,
1 Arithmetic and Logical Operations - Part II. Unsigned Numbers Addition in unsigned numbers is the same regardless of the base. Given a pair of bit sequences.
ECE 4110– Sequential Logic Design
ADDERS Half Adders Recall that the basic rules of binary addition are as indicated below in Table 2-9. A circuit known as the half-adder carries out these.
Copyright 1995 by Coherence LTD., all rights reserved (Revised: Oct 97 by Rafi Lohev, Oct 99 by Yair Wiseman, Sep 04 Oren Kapah) IBM י ב מ 10-1 The ALU.
King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department.
Spring 2002EECS150 - Lec12-cl3 Page 1 EECS150 - Digital Design Lecture 12 - Combinational Logic Circuits Part 3 March 4, 2002 John Wawrzynek.
Multiplication of signed-operands
Digital Kommunikationselektronik TNE027 Lecture 2 1 FA x n –1 c n c n1- y n1– s n1– FA x 1 c 2 y 1 s 1 c 1 x 0 y 0 s 0 c 0 MSB positionLSB position Ripple-Carry.
Computer Arithmetic and the Arithmetic Unit Lesson 2 - Ioan Despi.
Lecture 6: Multiply, Shift, and Divide
EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 8 Arithmetic.
Digital Logic Design (CSNB163)
Csci 136 Computer Architecture II – Multiplication and Division
CPEN Digital System Design
Division Quotient Divisor Dividend – – Remainder.
Chapter 8 Computer Arithmetic. 8.1 Unsigned Notation Non-negative notation  It treats every number as either zero or a positive value  Range: 0 to 2.
UNIT 2. ADDITION & SUBTRACTION OF SIGNED NUMBERS.
Multipliers. More complicated than addition accomplished via shifting and addition More time and more area Multiplication What should be the length of.
1 Lecture 5Multiplication and Division ECE 0142 Computer Organization.
Week 1(Number System) Muhammad Ammad uddin Logic Design Lab I (CEN211)
William Stallings Computer Organization and Architecture 8th Edition
Computer System Design Lecture 3
More Binary Arithmetic - Multiplication
Multiplication and Division basics
Combinational Circuits
Integer Multiplication and Division
MIPS mul/div instructions
CHAPTER 1 INTRODUCTION NUMBER SYSTEMS AND CONVERSION
UNIVERSITY OF MASSACHUSETTS Dept
Morgan Kaufmann Publishers
Montek Singh Nov 8, 2017 Lecture 12
Multiplication & Division
Multipliers Multipliers play an important role in today’s digital signal processing and various other applications. The common multiplication method is.
Principles & Applications
Digital Systems Section 14 Registers. Digital Systems Section 14 Registers.
King Fahd University of Petroleum and Minerals
CSCI206 - Computer Organization & Programming
Topic 3c Integer Multiply and Divide
Unsigned Multiplication
Computer Organization and Design
Arithmetic Logical Unit
Computation in Other Bases
ECEG-3202 Computer Architecture and Organization
12/7/
October 15 Chapter 4 – Multiplication/Division Go to the State Fair!
Addition and multiplication
Montek Singh Mon, Mar 28, 2011 Lecture 11
Addition and multiplication
More Arithmetic: Multiplication, Division, and Floating-Point
Appendix J Authors: John Hennessy & David Patterson.
October 5 Register to vote! Go to the State Fair! (15-24 October)
Number Representation
Instruction execution and ALU
1 Lecture 5Multiplication and Division ECE 0142 Computer Organization.
Presentation transcript:

Reading: Study Chapter 3.1-3.4 (including Booth coding) Binary Multipliers The key trick of multiplication is memorizing a digit-to-digit table… Everything else was just adding × 1 2 3 4 5 6 7 8 9 10 12 14 16 18 15 21 24 27 20 28 32 36 25 30 35 40 45 42 48 54 49 56 63 64 72 81 × 1 You’ve got to be kidding… It can’t be that easy Reading: Study Chapter 3.1-3.4 (including Booth coding)

Binary Multiplication 1 X The “Binary” Multiplication Table Binary multiplication is implemented using the same basic longhand algorithm that you learned in grade school. Hey, that looks like an AND gate A3 A2 A1 A0 x B3 B2 B1 B0 A3B0 A2B0 A1B0 A0B0 AjBi is a “partial product” A3B1 A2B1 A1B1 A0B1 A3B2 A2B2 A1B2 A0B2 + A3B3 A2B3 A1B3 A0B3 Multiplying N-digit number by M-digit number gives (N+M)-digit result Easy part: forming partial products (just an AND gate since BI is either 0 or 1) Hard part: adding M, N-bit partial products

Multiplication: Implementation S t a r t D o n e 1 . T s t M u l i p r a A d m c h P g 2 S f b 3 M u l t i p l i e r = 1 M u l t i p l i e r = t N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s

Second Version S t a r t M u l t i p l i c a n d D o n e 1 . T s t M u a A d m c h f P g 2 S b 3 3 2 b i t s M u l t i p l i e r = 1 M u l t i p l i e r = M u l t i p l i e r 3 2 - b i t A L U S h i f t r i g h t 3 2 b i t s S h i f t r i g h t P r o d u c t C o n t r o l t e s t W r i t e 6 4 b i t s i f t t h e M u l t i p l i e r r e g i s t e r r i g h t 1 b i t N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s

Example for second version 0010 1100 0001 0110 0010 0001 0000 Test true shift right 4 0001 1000 0000 1100 0010 0001 Test false shift right 3 0011 0000 0001 1000 0101 0010 2 0010 0000 0001 0000 1011 0101 1 0000 0000 1011 Initial Product Multiplicand Multiplier Step Iteration

Final Version S t a r t D o n e 1 . T s t P r d u c a A m l i p h f g 2 S b 3 M u l t i p l i c a n d 3 2 b i t s P r o d u c t = 1 P r o d u c t = 3 2 - b i t A L U S h i f t r i g h t C o n t r o l P r o d u c t W r i t e t e s t 6 4 b i t s The trick is to use the lower half of the product to hold the multiplier during the operation. N o : < 3 2 r e p e t i t i o n s e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s

What about the sign? Positive numbers are easy. How about negative numbers? Please read Booth coding in textbook

Faster Multiply A1 & B A0 & B A2 & B A3 & B A31 & B P32-P63 P2 P1 P0

Simple Combinational Multiplier tPD = 10 * tPD,FA not 16 HA A Co B S tPD = (2*(N-1) + N) * tPD,FA Components N * HA N(N-1) * FA The Logic of a Half- Adder CO A B S NB: this circuit only works for nonnegative operands

Carry-Save Combinational Multiplier These Adders can be removed, and the AND gate outputs tied directly to the Carry inputs of the next stage. Observation: Rather than propagating the sums across each row, the carries can instead be forwarded onto the next column of the following row This small improvement in performance hardly seems worth the effort, however, this design is easier to pipeline. tPD = 8 * tPD,FA tPD = (N+N) * tPD,FA Components N * HA N2 * FA

Division Start 1. Subtract Divisor from the Remainder leave the result in the Remainder >=0 <0 Test Remainder Restore Remainder by adding Divisor Shift Quotient to the left set its rightmost bit = 0 Shift Quotient to the left set its rightmost bit = 1 Shift Divisor Register right 1 bit Repeat 33 times