Assembly Language (CSW 353) Chapter 2: IA-32 Processor Architecture Assembly Language

General Concepts Basic microcomputer design Instruction execution cycle Reading from memory How programs run 2 Assembly Language

Basic Microcomputer Design Clock synchronizes CPU operations control unit (CU) coordinates sequence of execution steps ALU performs arithmetic and bitwise processing 3

Basic Microcomputer Design Memory Storage Unit: primary memory I/O Devices: Input/Output devices Data bus: moves data between memory/i/o and registers 4

Basic Microcomputer Design Control bus: determines where data comes from and goes, and ALU activities Address bus: selects where data comes from or goes to 5

Clock synchronizes all CPU and BUS operations machine (clock) cycle measures time of a single operation clock is used to trigger events 6

Instruction Execution Cycle Fetch instruction Decode Fetch operands Execute Store output Loop fetch next instruction advance the program counter (PC) decode the instruction if memory operand needed, read value from memory execute the instruction if result is memory operand, write result to memory continue loop 7

The ability to overlap execution of different instructions at the same time. Multi-Stage Pipeline Pipelining makes it possible for processor to execute instructions in parallel Instruction execution divided into discrete stages Example of a non- pipelined processor. Many wasted cycles. 8

More efficient use of cycles, greater throughput of instructions: Pipelined Execution More efficient use of cycles, greater throughput of instructions: The number of instructions that complete in a span of time. For k stages and n instructions, the number of required cycles is: k + (n – 1) 9

Wasted Cycles (pipelined) When one of the stages requires two or more clock cycles, clock cycles are again wasted. For k stages and n instructions, the number of required cycles is: k + (2n – 1) 10

Superscalar A superscalar processor has multiple execution pipelines. In the following, note that Stage S4 has left and right pipelines (u and v). For k stages and n instructions, the number of required cycles is: k + n 11

Reading from Memory Cycle 1: address placed on address bus Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: Cycle 1: address placed on address bus Cycle 2: Read Line (RD) set low 12

Reading from Memory Cycle 3: CPU waits one cycle for memory to respond Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: Cycle 3: CPU waits one cycle for memory to respond Cycle 4: Read Line (RD) goes to 1, indicating that the data is on the data bus 13

Cache Memory High-speed expensive static RAM both inside and outside the CPU. Level-1 cache: inside the CPU Level-2 cache: outside the CPU Cache hit: when data to be read is already in cache memory Cache miss: when data to be read is not in cache memory. 14

How a Program Runs 15

Multitasking Operating System can run multiple programs at the same time. Multiple threads of execution within the same program. 16

Multitasking Scheduler utility assigns a given amount of CPU time to each running program task. Rapid switching of tasks gives illusion that all programs are running at once the processor must support task switching. 17

IA-32 Processor Architecture Short for "Intel Architecture, 32-bit", also called i386 is the 32-bit version of the x86 instruction set architecture (ISA), first implemented in the Intel 80386 microprocessors in 1985 IA-32 Processor Architecture Modes of operation Basic execution environment Floating-point unit Intel Microprocessor history 18

Modes of Operation Real-address mode Allows the microprocessor to address only the first 1MB of memory 8086, 8088 can only operate in the real mode the ability to switch into other modes native MS-DOS programs can cause the operating system to crash 19

Modes of Operation Protected mode Allows the access to data and programs located above the first 1MB of memory 80286 and above operate in either the real or protected mode native mode (Windows, Linux) programs are given separate memory areas named segments a portion of memory that has been restricted for use with a current running process 20

Modes of Operation Virtual-8086 mode System management mode hybrid of Protected Windows XP can execute multiple separate virtual-8086 sessions at the same time System management mode provides power management, system security, diagnostics 21

Basic Execution Environment Addressable memory General-purpose registers Index and base registers Specialized register uses Status flags Floating-point, MMX, XMM registers 22

Addressable Memory Protected mode Real-address and Virtual-8086 modes 4 GB 32-bit address Real-address and Virtual-8086 modes 1 MB space 20-bit address 23

Registers General Purpose Special Registers Index Registers AH AL Index Registers Accumulator AX Instr Pointer IP EAX EIP Stack Pointer SP BH BL Flags Base FLAG ESP BX EFLAG Base Pointer BP EBX EBP CH CL Count Segment Registers Dest Index DI CX EDI ECX CS Code Segment Source Index SI DH DL Data DS Data Segment ESI DX EDX SS Stack Segment ES Extra Segment FS GS 24

General-Purpose Registers They are the one we use most of the time Most of the instructions perform on these registers. They all can be broken down into 16 and 8 bit registers. Accumulator (AH,AL,AX,EAX) Accumulates results from mathematical calculations Base (BH,BL,BX,EBX) Points to memory locations 25

General-Purpose Registers Count (CL,CH,CX,ECX) Counter used typically for loops Can be automatically incremented/decremented Data (DL,DH,DX,EDX) Data used in calculations 26

Accessing Parts of Registers Use 8-bit name, 16-bit name, or 32-bit name Applies to EAX, EBX, ECX, and EDX 27

Index Registers SP, ESP BP, EBP Stack pointer They some time used with a segment register to point to far address in a 1Mb range. The register with an "E" prefix can only be used in protected mode. SP, ESP Stack pointer BP, EBP is used by high-level languages to reference function parameters and local variables on the stack. 28

Index Registers SI, ESI, DI, EDI Source/Destination registers Point to the starting address of a string/array Used to manipulate strings and similar data types 29

Segment Registers CS (code segment) DS (data segment) They hold the segment address of various items. They can only be set by a general register or special instructions. CS (code segment) Points to the memory area where your program’s instructions are stored DS (data segment) Points to the memory area where your program’s data is stored 30

Segment Registers SS (stack segment) ES,FS,GS (additional segments) Indicate base addresses of pre-assigned memory areas named segments SS (stack segment) Points to the memory area where your stack is stored ES,FS,GS (additional segments) They can be used to point to additional data segments, if necessary 31

Special Registers EIP – Instruction pointer EFLAGS – Flags register Points always to the next instruction that the processor is going to execute Only changed indirectly by branching instructions EFLAGS – Flags register status and control flags each flag is a single binary bit contains individual bits set by different operations (e.g. carry, overflow, zero) Used massively with branch instructions 32

Status Flags Carry (C) Overflow (O) Sign (S) Status of carry or borrow signed arithmetic out of range Sign (S) result is negative 33

Status Flags Zero (Z) Auxiliary Carry (A) Parity (P) result is zero carry from bit 3 to bit 4 Parity (P) Set if the least-significant byte in the result contains an even number 34

Status Flags (Cont) Interrupt (I) Supervisor (S) indicates that an interrupt is currently active Supervisor (S) Indicates that CPU is operating in supervisor mode 35

Floating-Point, MMX, XMM Registers It is specially designed to carry out operations on floating point numbers, i.e. addition, subtraction, ... Some systems (i.e. microcode-based architectures) can also perform various functions such as exponential or trigonometric calculations. One or more FPUs (Floating-Point Units) may be integrated with the CPU. 36

Floating-Point, MMX, XMM Registers Eight floating-point data registers ST(0), ST(1), . . . , ST(7) arranged in a stack used for all floating-point arithmetic Eight 64-bit MMX registers Support special instructions called SIMD (Single-Instruction, Multiple-Data) Eight 128-bit XMM registers streaming SIMD extensions to the instruction set. 37

Program Execution Speed When designing a processor the most important thing to consider is the program execution speed. Modified by Dr. R. Orban

RISC and CISC In order to increase the processor speed – reducing the time needed to execute an instruction – one can either: Reduce the number of machine instructions or Reduce number of clock cycles needed to execute an instruction. Modified by Dr. R. Orban

RISC and CISC Processors designed using the first approach (Reduce the number of machine instructions) are called Complex Instruction Set Computers (CISC) processors. Processors designed using the second (Reduce number of clock cycles needed to execute an instruction) approach are called Reduced Instruction Set Computers (RISC) processors.  Modified by Dr. R. Orban

CISC and RISC CISC – complex instruction set large instruction set high-level operations requires microcode interpreter Examples: Intel 8086 family 41

CISC and RISC RISC – reduced instruction set simple, atomic instructions small instruction set directly executed by hardware Examples: ARM (Advanced RISC Machines) 42

IA-32 Memory Management Real-address mode Calculating linear addresses Protected mode Multi-segment model Paging 43

Real-Address mode 1 MB RAM maximum addressable Application programs can access any area of memory Single tasking Supported by MS-DOS operating system 44

Segmented Memory Memory segmentation is the division of a computer's primary memory into segments or sections. In a computer using segmentation, a reference to a memory location includes a value that identifies a segment and an offset (memory location) within that segment. 45

Segmented Memory In the Intel 8086 processor, the 16-bit registers could not hold 20-bit addresses. To represent segment values, the last zero of the segment address is dropped. Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset. linear addresses one segment 46

Calculating Linear Addresses Given a segment address, multiply it by 10 (add a hexadecimal zero), and add it to the offset Example: Convert 08F1:0100 to a linear address Multiply Seg. by ‘1O’ Seg. Ofs. Adjusted Segment value: 0 8 F 1 0 Add the offset: 0 1 0 0 Linear address: 0 9 0 1 0 47

Protected Mode (1 of 2) 4 GB addressable RAM (00000000 to FFFFFFFF) h Each program assigned a memory partition which is protected from other programs Designed for multitasking Supported by Linux & MS-Windows 48

Macro Assembler from Microsoft Protected mode (2 of 2) most of the memory management and Interrupt Service Routines are controlled through tables of descriptors. Each descriptor stores information about a single object (e.g. a service routine, a task, a chunk of code or data, …) the CPU might need. Segment descriptor tables Program structure code, data, and stack areas CS, DS, SS segment descriptors global descriptor table (GDT) MASM Programs use the Microsoft flat memory model Macro Assembler from Microsoft OS creates when switching the processor into protected mode during boot up. It contains entries (segment descriptors) that point to segments. or linear memory model refers to a memory addressing paradigm in which "memory appears to the program as a single contiguous address space." 49

Flat Segment Model Single global descriptor table (GDT). All segments mapped to entire 32-bit address space 50

Multi-Segment Model Each program has a local descriptor table (LDT) contain memory segments which are private to a specific program each task can have its own LDT and that the processor will automatically switch to the right LDT when you use hardware task switching. Each program has a local descriptor table (LDT) holds descriptor for each segment used by the program 51

Paging Supported directly by the CPU Divides each segment into (4KB) 4096- byte blocks called pages Paging permits the total memory used by all programs running at the same time to be much larger than the computer’s physical memory. 52

Paging 53

Paging Part of running program is in memory, part is on disk Virtual memory manager (VMM) – OS utility that manages the loading and unloading of pages Page fault – issued by CPU when a page must be loaded from disk 54

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