Day 14: October 8, 2010 Performance ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 14: October 8, 2010 Performance Penn ESE370 Fall2010 -- DeHon
Previously Delay as RC-charging Transistor Gate Capacitance Drive Current As a function of geometry (W/L) Gate Topology Delay Penn ESE370 Fall2010 -- DeHon
Today Miller Effect Sizing Large Fanout Data Dependent Delay Asymmetry of Inputs Impact of P & N Mobility differences Large Fanin Penn ESE370 Fall2010 -- DeHon
Gate-Drain Capacitance What is the voltage across Vin—V2 When Vin=Vdd When Vin=Gnd What is DV across Vin—V2 when Vin switches from Vdd to Gnd? Penn ESE370 Fall2010 -- DeHon
Miller Effect For an inverting gate Capacitance between input and output must swing 2 Vhigh Or…acts as double-sized capacitor Penn ESE370 Fall2010 -- DeHon
Transistor Sizing What happens to Ids as a function of W? What happens to Cg as a function of W? Conclude: faster transistors present more load on their inputs Penn ESE370 Fall2010 -- DeHon
First Order Delay R0 = Resistance of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Rdrive = R0/W Cg = WC0 Penn ESE370 Fall2010 -- DeHon
Inverter Sizing What is the impact of the delay on the middle inverter if double size of all the transistors? Penn ESE370 Fall2010 -- DeHon
How Size Equal Rise and Fall mn=500cm2/Vs, mp=200cm2/Vs Rdrive=R0/2 Penn ESE370 Fall2010 -- DeHon
Sample Gate Internal stages have delay External depend on load Assume (guarantee) all inputs same load Penn ESE370 Fall2010 -- DeHon
Large Fanout What is delay if must drive fanout=100? Penn ESE370 Fall2010 -- DeHon
What Delay? What is delay here? Penn ESE370 Fall2010 -- DeHon
How Size How size transistors to minimize delay? Penn ESE370 Fall2010 -- DeHon
Try again What is the delay here? Penn ESE370 Fall2010 -- DeHon
…and Again Delay here? Penn ESE370 Fall2010 -- DeHon
Lesson Don’t drive large fanout with a single stage Must scale up over a number of stages …but not too many Exact number will be technology dependent Penn ESE370 Fall2010 -- DeHon
Lecture ended here Penn ESE370 Fall2010 -- DeHon
Gates Penn ESE370 Fall2010 -- DeHon
Data Dependent Delay Resistance depends on input values delay depends on input data Penn ESE370 Fall2010 -- DeHon
How Size Equalize rise/fall times Rdrive=R0/2 Penn ESE370 Fall2010 -- DeHon
How Size For equal rise fall Rdrive=R0/2 Penn ESE370 Fall2010 -- DeHon
Input Load Input capacitance in each case? Penn ESE370 Fall2010 -- DeHon
Observe Ratio of Input Load Capacitance to Output Drive Strength Differs with gate function Some gates give more drive per capacitive load we pay Penn ESE370 Fall2010 -- DeHon
Which Implementation is Faster? Penn ESE370 Fall2010 -- DeHon
Take Away? Penn ESE370 Fall2010 -- DeHon
Input (A)Symmetry If one input is known to be later than other, does it matter where it goes? Penn ESE370 Fall2010 -- DeHon
How Size Equalize rise/fall times Rdrive=R0/2 Penn ESE370 Fall2010 -- DeHon
Increasing Fanin What happens to input capacitance as fanin (k) increases Keeping output drive the same E.g. Rdrive=R0/2 k-input nand gate has input capacitance: Penn ESE370 Fall2010 -- DeHon
Fanin Gates slow down with fanin Less drive per input capacitance Penn ESE370 Fall2010 -- DeHon
Which is fastest? nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 Penn ESE370 Fall2010 -- DeHon
Lesson Large gates are slow / inefficient High capacitive load / drive strength Small gates can be inefficient Need many stages Staging over moderate size gates minimizes delay Exact size will be technology dependent Penn ESE370 Fall2010 -- DeHon
Admin Project 1 Out Fall Break on Monday Next Lecture Wednesday 2 week assignment Optimizing Performance Recommended milestones for next week Fall Break on Monday No class Next Lecture Wednesday Penn ESE370 Fall2010 -- DeHon
Ideas First order reason in R0C0 units Gates have different efficiencies Drive strength per unit input capacitance Greater N mobility (than P) favors nand over nor Large fanin and fanout slow gates Decompose into stages …but not too much Penn ESE370 Fall2010 -- DeHon