Synthesis and Exploration of Multi-Level, Multi-Perspective Architectures of Automotive Embedded Systems Jordan Ross, Alexandr Murashkin, Jia Hui Liang,

Slides:



Advertisements
Similar presentations
Dynamic Topology Optimization for Supercomputer Interconnection Networks Layer-1 (L1) switch –Dumb switch, Electronic “patch panel” –Establishes hard links.
Advertisements

Fault Detection in a HW/SW CoDesign Environment Prepared by A. Gaye Soykök.
Midterm Notes Modeling and Best Decision SAILS & Manugistics Powerpoint Slides Presentations.
Winter-Spring 2001Codesign of Embedded Systems1 Introduction to HW/SW Co-Synthesis Algorithms Part of HW/SW Codesign of Embedded Systems Course (CE )
Computational Methods for Management and Economics Carla Gomes Module 4 Displaying and Solving LP Models on a Spreadsheet.
Computer Science Open Research Questions Adversary models –Define/Formalize adversary models Need to incorporate characteristics of new technologies and.
A Federation Architecture for DETER Ted Faber, John Wroclawski, Kevin Lahey, John Hickey University of Southern California Information Sciences Institute.
Jon Perez, Mikel Azkarate-askasua, Antonio Perez
Intro to Network Design
Assessing the influence on processes when evolving the software architecture By Larsson S, Wall A, Wallin P Parul Patel.
Hardware-software Interface Xiaofeng Fan
Cupid: A Smart Development Environment for Earth System Models Rocky Dunlap research sponsored by NASA/ROSES 1.
6/16/2008 The eXpress Maintenance Module DSI International November, 2015.
John D. McGregor Architecture Evaluation
Wireless sensor and actor networks: research challenges
1 May-2014 Automotive Protocols & Standards. 2 CAN (Controller Area Network)  Overview Controller Area Network is a fast serial bus designed to provide.
Improving System Availability in Distributed Environments Sam Malek with Marija Mikic-Rakic Nels.
Technician Table Editor Company: DVTel Academic advisor: Professor Ehud Gudes Technical advisor: Menny Even Danan Team: Olga Peled Doron Avinoam.
Copyright © Richard N. Taylor, Nenad Medvidovic, and Eric M. Dashofy. All rights reserved. Deployment and Mobility Software Architecture Lecture 12.
1 Patron Blocks - Librarian assigned and system assigned Senior Librarian Yoel Kortick.
Enhancements for Voltaire’s InfiniBand simulator
Building Intercom Solution
LEYARD DIRECTLIGHT LED VIDEO WALL SYSTEM
Chapter 4 PowerPoint Spreadsheet Analysis.
Wireless Sensor Networks
Sensors Control Systems with Flowol.
Collect and share knowledge
T-Share: A Large-Scale Dynamic Taxi Ridesharing Service
ONYX 12.2.
Writing simple Java Web Services using Eclipse
Brian Leonard ブライアン レオナルド
Distributed Real-Time Embedded Video Processing
NETWORK TOPOLOGIES There are three basic configurations used to connect computers they are the Bus Ring Star.
Network Configurations
Exploring Concentration and Channel Slicing in On-chip Network Router
Introduction to Networks
Furniture Assembly using Augmented Reality
Reseller Option Kit (ROK)
Period Optimization for Hard Real-time Distributed Automotive Systems
John D. McGregor Quality attributes
Controller Area Network (CAN) Training
Synthesis and Exploration of Multi-Level, Multi-Perspective Architectures of Automotive Embedded Systems Jordan A. Ross June 10th, 2016.
Bluetooth Based Smart Sensor Network
Extending IP to Low-Power, Wireless Personal Area Networks
New horizons in the artificial vision
Phase 4: Prepare a Timetable and Implementation Plan
Chapter 20 Object-Oriented Analysis and Design
Architectures of distributed systems Fundamental Models
Carlos J. Bernardos, Alain Mourad, Akbar Rahman
Chapter 5 Architectural Design.
Analysis models and design models
Wireless Sensor Network - course: Project to investigate requirements and applications using wireless sensor networks on a construction site Ykä Marjanen.
Architectures of distributed systems Fundamental Models
An Introduction to Software Architecture
Collect and share knowledge
Vanilson Burégio The Battlefield Control System – The First Case Study in Applying the ATAM Chapter 4 of: Clements, Paul et al., Evaluating.
Resilient Information Architecture Platform for Smart Grid
Delivering great hardware solutions for Windows
Architectures of distributed systems
Internet Engineering Course
Software Architecture
Mathias Johanson, Jonas Jalminger Boel Nelson, Tomas Olovsson
Design Yaodong Bi.
Architectures of distributed systems Fundamental Models
*Internal Synthesizer Flow *Details of Synthesis Steps
SCCM in hybrid world Predrag Jelesijević Microsoft 7/6/ :17 AM
Adaptive Traffic Control
Software Development Process Using UML Recap
IT Management, Simplified
How to RFA (Request for approval)
Presentation transcript:

Synthesis and Exploration of Multi-Level, Multi-Perspective Architectures of Automotive Embedded Systems Jordan Ross, Alexandr Murashkin, Jia Hui Liang, Michał Antkiewicz, Krzysztof Czarnecki September 20th, 2017

Background & Motivation Wants to design the power window E/E architecture Design Decisions Design Constraints Design Objectives With Respect To Emily Creates E/E Architectural Model with Variability Synthesize Candidate Architectures Visualizes Candidates and Tradeoffs TODO: Update figure: Change John to Emily (everywhere) Change how I use the downward arrows Change wording to align with new paper definitions Where does synthesis fit it? Expresses Possible Candidate Architectures

Wants to design the power window E/E architecture Design Decisions Design Constraints Design Objectives With Respect To Emily Creates E/E Architectural Model with Variability Synthesize Candidate Architectures Visualizes Candidates and Tradeoffs Expresses Possible Candidate Architectures

Our Reference Model for Early Design System Perspectives Feature Model Functional Analysis Architecture … Variability Latency Mass Parts Cost Warranty Parts Cost Multi-Layer Hardware Design Architecture Make sure to go into details about the layers Device Node Classification Power Topology Communication Topology Multi-Perspective

Capturing Variability System Feature Model Functional Analysis Architecture Hardware Design Architecture Device Node Classification Communication Topology Power Topology Feature Presence Function Presence Function Connector Presence Function Implementation Choice Function Deployment Function Connector Deployment Device Node Type Device Node Presence Connector Source and Target Connector Presence Bus Type Connector Presence Connector Endpoints

Emily’s Power Window Example Driver PW Basic Up Down Express Up Express Express Down DriverWinSysFAA WinSwitch WinMotor CurrentSensor WinArbiter WinControl PinchDetectionFAA PositionSensor PinchDetection position object localWinReq winReq winCmd current HW HW/SW SW Put a lengend for the FAA Feature Model Legend Feature Optional Mandatory Exclusive Features

Capturing Latency System Feature Model Functional Analysis Architecture Hardware Design Architecture Device Node Classification Communication Topology Power Topology Form timing chains using functions and function connectors Assign latencies to functional devices and analysis functions Assign message sizes to function connectors Deployed to smart node affects function latency Deployed to hardware connector affects function connector latency Make note that this is not a constraint. Just stating some properties about the system. Assign speed factors to smart nodes Different communication connectors have different transfer rates.

Capturing Mass, Parts Cost, and Warranty Parts Cost RQ1: What aspects of our reference model are unique and not found in current meta-models for E/E architecture? Or are found but not supported by reasoning? System Feature Model Functional Analysis Architecture Hardware Design Architecture Device Node Classification Communication Topology Power Topology Mass Assign lengths to hardware connectors Multiplicative factor for unit length mass for each connector type. Assign mass to device nodes. Cost Multiplicative factor for unit length cost for each connector type. Assign cost to device nodes. Warranty Cost Assign replacement cost to device nodes. Assign failure rate in PPM

Wants to design the power window E/E architecture Design Decisions Design Constraints Design Objectives With Respect To Emily Creates E/E Architectural Model with Variability Synthesize Candidate Architectures Visualizes Candidates and Tradeoffs Expresses Possible Candidate Architectures

Some Example Design Exploration Scenarios Emily would like to investigate the possibility of adding a dedicated ECU to each door (we call the door module). Precisely, she would like to find out if it is a cost effective solution while meeting the requirements for mass and latency. Emily is tasked with designing the power window for a higher end car in which cost is irrelevant but mass should be minimized, she would like to explore the possible designs. Additionally, since it’s a high end car, all features should be included. Lastly, the end-to-end latency for pinch detection to react and reverse the motor should be less than 200 ms. Emily would like to minimize the cost, regardless of the features to support an “economy class” vehicle her company is rolling out. Is there an optimal car design that does include all features? OPTIONAL: - Include why manually exploring candidates does not work as well.

What Design Decisions Can We Make? System Feature “ExpressUp” is in the architecture. “WinArbiter” function is implemented in hardware. The “Switch” device node is smart The “DoorModule” device node is present in the architecture The “winCmd” function connector uses the “localDoorBus” bus connector to communicate. …. Feature Model Functional Analysis Architecture Variability Hardware Design Architecture Device Node Classification Power Topology Communication Topology Combine the system model with variability

What Design Constraints and Objectives Can We Have? System Feature Model The end to end latency for the timing chain from the “WinSwitch” function to the “WinMotor” function is less than 500 ms. Minimize the total mass of the system … Functional Analysis Architecture Latency Mass Parts Cost Warranty Parts Cost Hardware Design Architecture Device Node Classification Power Topology Communication Topology Combine the system model with quality perspectives

Generalizing the Possible Specifications make sure to state that this is not the complete possibilities I need to update this.

Example RQ2: Are there design exploration scenarios in which considering our reference model we can consider while others can not? Emily is tasked with designing the power window for a higher end car in which cost is irrelevant but mass should be minimized, she would like to explore the possible designs. Additionally, since its a high end car, all features should be included. Lastly, the end-to-end latency for pinch detection to react and reverse the motor should be less than 200 ms. Feature “ExpressUp” is in the architecture AND The end-to-end latency for timing chain PinchDetection_TC must be less than 200 ms AND Minimize the total mass of the architecture TODO: Add animation.

Wants to design the power window E/E architecture Design Decisions Design Constraints Design Objectives With Respect To Emily Creates E/E Architectural Model with Variability Synthesize Candidate Architectures Visualizes Candidates and Tradeoffs Now we want to visualize. To do this we need to now discuss what we used to encode the model and encode the specifications Expresses Possible Candidate Architectures

How Is This All Possible? Wants to design the power window E/E architecture Emily Creates E/E Architectural Model with Variability Chocosolver Synthesize Candidate Architectures Visualizes Candidates and Tradeoffs Clafer Web Tools

Visualizing Tradeoffs With Clafer Web Tools TODO: Show an example visualization for the design specification.

Case Studies https://github.com/gsdlab/ClaferCaseStudies/tree/master/PlainClafer/Automotive/ BodyDomain

Power Window Feature Model Driver Power Window Basic Up / Down Express Up Express Down Passenger Power Window Basic Up / Down implies Show a snippet of clafer here

Door Locks Feature Model Outside Door Handle Sensor Basic Door Locks Remote Key Access Passive Key Entry Lock Switch Position Speed Smart Lock Individual Lock Switch Central Lock Switch implies Button Sensor Capacitive Sensor

Model Sizes Single Door Power Window Two Door Power Window Central Door Locks Features 3 (2) 6 (4) 7 (6) Analysis Functions 3 (1) 6 (2) Functional Devices 4 (1) 9 (2) 33 (15) Deployment Configurations 64 4096 96 Function Connectors 7 (4) 33 (18) Device Nodes 10 (3) 21 (14) Discrete/Analog Connectors 13 (13) 18 (18) 34 (30) Bus Connectors 1 (1) 2 (1) Number of Variants 32 thousand > 959 million ~ 2 thousand Single – 32,000 Two door – Over 959 million candidates Add row for the number of candidates.

How Does Our Approach Compare? Dedicated door ECU vs. no door ECU RQ1: What aspects of our reference model are unique and not found in current meta-models for E/E architecture? Or are found but not supported by reasoning? RQ1 Answer: Features, variability at all layers, function implementation, discrete/analog connectors, and power topology Possible to implement express up feature Dumb vs. Smart AAOL – Automotive Architecture Optimization Language High-end car Economy car Distributed vs. Centralized

A Closer Look at the Economy Scenario Emily would like to minimize the cost, regardless of the features to support an “economy class” vehicle her company is rolling out. Is there an optimal car design that does include all features? RQ2: Are there design exploration scenarios in which considering our reference model we can consider while others can not? RQ2 Answer: Yes!

Looking at the Chocosolvers Performance RQ4: Is it even feasible to ask the individual design decisions, constraints, and objectives shown earlier? RQ4 Answer: The majority are feasible however, there are issues in when trying to find all optimal solutions. TODO: Move tables

Looking at the Chocosolvers Performance RQ5: Is it feasible to ask the 6 design scenarios when considering the single and two door power window model? RQ5 Answer: It is feasible when considering the single door power window, however not for the two door case.

Conclusion Presented a reference model for early design of E/E architectures. Showed how the reference model can be used to model a power window architecture that expresses millions of candidate designs. Highlighted where our approach surpasses current tooling. Room for future work… Improve performance of analysis Model simplification Solvers Surrogate models Extending our reference model to accommodate fault tolerant architectures. Refining the early design candidates to detailed designs. ROI for design exploration tools. Adoption in practice Creating models Performance

Thanks for Listening! Questions?