Another Physical Layer – I2C Multi-mastered Send and receive Two wire (plus ground) Serial CSE 466 – Fall 2000 - Introduction - 1

CSE 466 – Fall 2000 - Introduction - 2 Terminology CSE 466 – Fall 2000 - Introduction - 2

CSE 466 – Fall 2000 - Introduction - 3 Physical Interface wired-and configuration CSE 466 – Fall 2000 - Introduction - 3

CSE 466 – Fall 2000 - Introduction - 4 Bit Transfer Transmitter (master or slave) sampled on both edges Master CSE 466 – Fall 2000 - Introduction - 4

CSE 466 – Fall 2000 - Introduction - 5 Who gets to be master The one who initiates a frame: A frame is: <Start><addr><data>…<data><Stop> OR <Start><addr><data>…<data><R_Start><addr><data>…<Stop> CSE 466 – Fall 2000 - Introduction - 5

CSE 466 – Fall 2000 - Introduction - 6 An I2C Byte Transfer MSB First MSB……………….LSB slave slave Tx Device Rx Device master CSE 466 – Fall 2000 - Introduction - 6

CSE 466 – Fall 2000 - Introduction - 7 A Complete Frame MSB……..LSB Addresses are 7 bits, LSB of address byte is Read/Write control. Determines whether master or slave becomes the transmitter CSE 466 – Fall 2000 - Introduction - 7

CSE 466 – Fall 2000 - Introduction - 8 Arbitration It is up to the failed master to try again when the bus is not busy. Seems like high address devices are low priority receivers…but I haven’t read this anywhere CSE 466 – Fall 2000 - Introduction - 8

CSE 466 – Fall 2000 - Introduction - 9 Interfacing to the Bus 8051 Electrical connection is fine. But the software is complex CSE 466 – Fall 2000 - Introduction - 9

CSE 466 – Fall 2000 - Introduction - 10 An alternative 8051 addr (1bit) A0 PCF 8584 I2C Bus Controller data (8 bits) P0 DB rst CK2 \CS \RD \WR Memory mapped device that handles bit level interface. Only do byte level stuff in software CSE 466 – Fall 2000 - Introduction - 10

Using the Bus Interface CSE 466 – Fall 2000 - Introduction - 11

CSE 466 – Fall 2000 - Introduction - 12 Slave Flow CSE 466 – Fall 2000 - Introduction - 12

CSE 466 – Fall 2000 - Introduction - 13 Slave Receiver Mode CSE 466 – Fall 2000 - Introduction - 13