Multioperand Addition Lecture 6 Multioperand Addition Modular Addition

Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 8, Multioperand Addition Chapter 7.6, Modular Two-Operand Adders

Applications of multioperand addition Inner product Multiplication n-1 n-1 p=a·x s =  x(i) y(i) =  p(i) i=0 i=0

Number of bits of the result S =  x(i) x(i) [0..2k-1] i=0 Smin = 0 Smax = n (2k-1) # of bits of S = log2 (Smax + 1) = = log2 (n (2k-1) + 1)  log2 n 2k = = k + log2 n

Serial implementation of multioperand addition

Adding 7 numbers in the binary tree of adders

Ripple-carry adders at levels i and i+1

Example: Adding 8 3-bit numbers

Ripple-Carry Carry Propagate Adder (CPA) ak-1 bk-1 a2 b2 a1 b1 a0 b0 ck c3 ck-1 c2 c1 c0 FA . . . FA FA FA sk-1 s2 s1 s0

Carry Save Adder (CSA) ak-1 bk-1 ck-1 a2 b2 c2 a1 b1 c1 a0 b0 c0 FA . . . FA FA FA ck sk-1 ck-1 s3 c3 s2 c2 s1 c1 s0

A Ripple-Carry vs. Carry-Save Adder

Operation of a Carry Save Adder (CSA) Example 24 23 22 21 20 x y z 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 s c 0 0 1 1 0 1 1 0 1 1 x+y+z = s + c

Carry propagate and carry-save adders in dot notation

Specifying full- and half-adder blocks in dot notation

Carry-save adder for four operands x3 x2 x1 x0 y3 y2 y1 y0 z3 z2 z1 z0 w3 w2 w1 w0 s3 s2 s1 s0 c4 c3 c2 c1 c4 s3 s2 s1 s0 ’ S5 S4 S3 S2 S1 S0

Carry-save adder for four operands ’ c4 ’ s3 ’ c3 ’ s2 ’ c2 ’ s1 ’ c1 ’

Carry-save adder for four operands x y z w CSA c s CSA c’ s’ CPA S

Carry-save adder for six operands Implementation of one-bit slice CSA tree

Tree of carry save adders reducing seven numbers to two

Addition of seven six-bit numbers in dot notation

Adding seven k-bit numbers: block diagram

Number of Inputs and Tree Height Relationship Between Number of Inputs and Tree Height h levels

Parameters of tree carry-save adders (1) Latency LatencyCSA = h(n)  TFA + LatencyCPA(k, n) Tree height for n operands Component Adders Widths typically close to k bits CSA k .. k + log2 n CPA  k + log2 n

Parameters of tree carry-save adders (2) Maximum number of inputs that can be reduced to two by an h-level tree, n(h) n(0) = 2 3 2 n(h) = n(h-1) n(1) = 3 n(2) = 4 n(3) = 6 n(4) = 9 n(5) = 13 n(6) = 19 3 2 3 2 2 ( )h-1 < n(h)  2 ( )h

Smallest height of the tree carry save adder Parameters of tree carry-save adders (3) Smallest height of the tree carry save adder for n operands, h(n) h(n) = 1 + h( ) 2 n 3 h(2) = 0 h(n)  log ( ) n 3 2 2

Wallace vs. Dadda Trees (1) Wallace trees Reduce the size of the final Carry Propagate Adder (CPA) Optimum from the point of view of speed Dadda trees Reduce the cost of the carry save tree Optimum (among the CSA trees) from the point of view of area

Wallace vs. Dadda Trees (2) Wallace reduces number of operands at earliest opportunity Goal of this is to have smallest number of bits for CPA adder However, sometimes having a few bits longer CPA adder does not affect the propagation delay significantly (i.e. carry-lookahead) Dadda seeks to reduce the number of FA and HA units May be at the cost of a slightly larger final CPA

5-to-3 Parallel Counter a+b+c+d+e = s0+s1+s2 a 0 1 0 1 0 b 1 1 0 1 1 c 24 23 22 21 20 a b c d e 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 s0 s1 s2 0 1 1 1 0 0 1 1 0 0 1 0 0 1 1 a+b+c+d+e = s0+s1+s2

Implementation of 1-bit of 5-to-3 parallel counter using single CLB slice of a Virtex FPGA

Carry Save Adder vs. 5-to-3 Parallel Counter b c d e w PC CSA CPA y=a+b+c+d+e mod 2w a b c d e s2 s1 s0 w w w w w CSA CSA CSA CPA w y=a+b+c+d+e mod 2w

Generalized Parallel Counters Fig. 8.17 Dot notation for a (5, 5; 4)-counter and the use of such counters for reducing five numbers to two numbers. Multicolumn reduction (5, 5; 4)-counter Unequal columns Generalized parallel counter = Parallel compressor (2, 3; 3)-counter

Related Question from the Last Year’s Exam

Pseudocode sum = 0 for i = 0 to 3 do sum = sum + A + B + C + D end for average = sum / 24

Design and analyze the multi-operand adder MADD shown above by C D S 8 4 MADD >>4 reset clk Reg sum average Design and analyze the multi-operand adder MADD shown above by Drawing the dot diagram of the operations performed by MADD. Drawing a block diagram of MADD using medium level components, such as full-adders and half-adders.