Guest Lecture by David Johnston CprE 281: Digital Logic Guest Lecture by David Johnston http://www.ece.iastate.edu/~alexs/classes/

Chapter 6 Synchronous Sequential Circuits CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © 2013

Administrative Stuff Homework 8 is due today.

It is due next Monday, Nov. 18th, @ 4pm. Administrative Stuff Homework 9 is out. It is due next Monday, Nov. 18th, @ 4pm.

Sequential Circuits CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © 2013

Previously Until recently, we were only implementing logic functions with combinational circuits. Downside: all inputs must be applied at once.

Motivation There are things that we cannot conveniently do with combinational circuits. Inputs pass into the circuit over time. Compute results in series, not parallel. So, our circuits need some kind of memory.

Motivational Example A Suppose we wanted a circuit to add together an arbitrary number of 32 bit integers.

Motivational Example A Downsides of combinational implementation. Hardware will always have a (finite) maximum number of parallel additions. The circuitry would get complicated and costly if we tried to support a large number of parallel additions.

Idea: We can make a circuit like this for loop. Some inspiration: int sum(List<int> Inputs): int acc = 0 for each i in Inputs: acc = acc + i return acc Idea: We can make a circuit like this for loop. Spread out the addition operations over time. Iterate towards the solution.

Accumulated result depends on both: previously computed result, acc current input, i Calculate sum in a circuit by a sequence of operations.

This is a kind of serial adder This is a kind of serial adder. We will describe an implementation of a serial adder in a future lecture.

Motivational Example B w z clock Suppose we want a real-time circuit to monitor whether a vehicle is going too fast.

Motivational Example B w z clock Inputs: Suppose w is asserted whenever the vehicle’s speed is above a certain threshold, and that an updated signal w stabilizes shortly after every active clock edge (and before the next one).

Motivational Example B w z clock Outputs: We need to design B so that z will be high whenever whenever w has been high for two or more of the most recent clock cycles.

Consider The Input Sequence:

Goal: We need to design B so that it “remembers” enough about the past inputs to decide what to output next.

Problem: We can’t explicitly store all previous inputs, since this would be costly and there will eventually be too many to store.

Idea: In this case, to decide what to output next, it is enough for our circuit to only “remember” the last input “observe” the current input

In general, next output depends on both: some pattern in the past inputs current input

Sequential Circuits: Key Ideas The current output depends on something about the preceding sequence of inputs (and maybe the current output). Using memory elements (i.e. flip-flops), we design the circuit to remember some relevant information about the prior inputs.

We need to try to keep our designs simple. Caution It is possible to do lots of wild things when we throw memory elements into the mix. We need to try to keep our designs simple.

Design Patterns: Combinational Circuits Remember how we used some standard design patterns to convert logic function specifications (e.g. truth tables) into combinational circuits: (Simplified) SOP (Simplified) POS Multiplexer Decomposition (Look-Up-Table) Results were regularly designed, easy to understand combinational circuits.

Design Patterns: Sequential Circuits We study design patterns leverage some of the power of sequential circuits while keeping both the design process and the resulting design simple. Moore Machine Mealy Machine

First Design Pattern: Moore Machines

Moore Machine: A Type of Finite State Machine (FSM) C: z = 1 Reset B: z = 0 A: z = 0 w = 1

Finite number of states (nodes). Discrete state transitions (edges). C: z = 1 Reset B: z = 0 A: z = 0 w = 1 Finite number of states (nodes). Discrete state transitions (edges). Only “in” one state at a time. One reset state Every state has an outgoing state transition for each possible input.

Key: Next state depends on both current state and current input C: z = 1 Reset B: z = 0 A: z = 0 w = 1 Key: Next state depends on both current state and current input

Key: Output only depends on current state. C: z = 1 Reset B: z = 0 A: z = 0 w = 1 Key: Output only depends on current state.

Does this satisfy the needs of our design? C: z = 1 Reset B: z = 0 A: z = 0 w = 1 Does this satisfy the needs of our design?

C: z = 1 Reset B: z = 0 A: z = 0 w = 1 In general, we need to start tracing from the beginning to know which state the FSM is in. It may not be clear from a short sequence of outputs.

What is the meaning of each state? C: z = 1 Reset B: z = 0 A: z = 0 w = 1 What is the meaning of each state?

What is a State? It is not really a memory of every past input. (We might run out of space to remember it all!) Rather, it is a characterization or snapshot of the pattern of inputs which have come before.

Moore Machine Implementation The state diagram is just an illustration to help us describe and reason about how the FSM will behave in each of its states. So, how do we turn it into a circuit?

Moore Machine Implementation W Memory Elements Combinational Combinational Z circuit circuit Clock Note: The W and Z lines need not be wires. They can be buses.

State Storage W Q(t+1) Flip-Flop Array Q(t) Combinational Combinational Z circuit circuit Clock Any usable “memory” of the preceding input sequence is encoded in the flip-flop array.

FSM States The Flip-Flop Array stores an encoding of the current state. Q(t) Q(t+1) Clock

State Encoding Each of the states in our design is identified by a distinct code. If we use 3 flip-flops, then the FSM can have up to 23 = 8 distinct states. So, when the flip-flop array contains the code 011, we say that the machine is in state 011.

Every active clock edge causes a state transition. Synchronous Design W Q(t+1) Flip-Flop Array Q(t) Combinational Combinational Z circuit circuit Clock Every active clock edge causes a state transition.

Synchronous Design W Q(t+1) Flip-Flop Array Q(t) Combinational Combinational Z circuit circuit Clock We expect the input signals to be stable before the active clock edge occurs.

Synchronous Design W Q(t+1) Flip-Flop Array Q(t) Combinational Combinational Z circuit circuit Clock There is a whole other class of sequential circuits which are asynchronous, but we will not study them in this course.

Modular Design W Next State Logic Q(t+1) Flip-Flop Array Q(t) Output Logic Z Clock Next State Logic: uses W and Q(t) as inputs to compute Q(t+1), the next state for the machine to transition into.

Modular Design Output Logic: Maps Q(t) to some output. W Next State Logic Q(t+1) Flip-Flop Array Q(t) Output Logic Z Clock Output Logic: Maps Q(t) to some output.

Implementing Our Example C: z = 1 Reset B: z = 0 A: z = 0 w = 1 We need to find both the next state logic and the output logic implied by this machine.

Next state Present Output state A A B B A C C A C 1 z w = w = 1 Reset B: z = 0 A: z = 0 w = 1 Next state Present Output state z w = w = 1 A A B B A C C A C 1

State Transition and Output Table Next state Present Output state z w = w = 1 A A B B A C C A C 1 We need to change the state labels to state encodings. There are three states, so let’s use two flip-flops.

We call y1 and y2 the present state variables. Next State Logic Output Logic z Y y 2 2 Clock We call y1 and y2 the present state variables. We call Y1 and Y2 the next state variables.

We need to find logic expressions for Y y 1 1 w Next State Logic Output Logic z Y y 2 2 Clock We need to find logic expressions for Y1(w, y1, y2), Y2(w, y1, y2), and z(y1, y2).

Next state Present Output state A A B B A C C A C 1 z w = w = 1 w = 1 A A B B A C C A C 1 Present Next state state w = 1 Output y Y 2 z A 00 01 B 10 C 11 dd d We arbitrarily chose these as our state encodings. We could have used others.

Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d Y 1 y y d 1 1 d Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d Y 2 y y 2 1 w 00 01 11 10 d 1 1 d 1 z y 1 y 2 1 1 1 d

y y 2 1 Ignoring don't cares Using don't cares w 00 01 11 10 d Y = wy y Y = wy y 1 1 2 1 1 2 1 1 d y y 2 1 w 00 01 11 10 d Y = wy y + wy y Y = wy + wy 2 1 2 1 2 2 1 2 1 1 d 1 = w ( y + y ) 1 2 y 1 y 2 1 z = y y z = y 1 2 2 1 1 d

t 1 2 3 4 5 6 7 8 9 10 Clock w y z

Design Steps: Obtain the specification of the desired circuit. Derive a state diagram. Derive the corresponding state table. Reduce the number of states if possible. Decide on the number of state variables. Choose the type of flip-flops to be used. Derive the logic expressions needed to implement the circuit.

Questions?

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