第四章 80386的存贮器和输入/输出接口 作业：P335 5,7,13,17,21,25,36,37,41,44,45,46,48,52,65 21:46

9.2 386 DX Microprocessor Flexible 32-bit Microprocessor 21:46 9.2 386 DX Microprocessor Flexible 32-bit Microprocessor Optimized for System Performance Pipelined Instruction Execution On-chip Address Translation Caches Dynamic Bus Sizing CHMOS(Complementary High-Performance Metal-Oxide-Semiconductor) III and CHMOS IV Technology approximately 275,000 Transistors more than twice that of the 80286 almost 10 times that of the 8086 132-pin Pin Grid Array (PGA) package See fig 9.2 : pin layout See fig 9.2 (b) : signal pin numbering 80386SX : 100-lead Plastic quad flat package(PQFP) - surface mount installation

21:46 Pin Layout P290. Fig 9.2a

Signal Pin Numbering P291. Fig 9.2b 21:46 Signal Pin Numbering P291. Fig 9.2b

21:46 9.3 Interfaces of the 80386DX Block Diagram of the 80386

Interfaces of the 80386DX Four interfaces Signals of the 80386DX 21:46 Interfaces of the 80386DX Four interfaces Memory/IO interface Interrupt Interface DMA Interface Coprocessor Interface Signals of the 80386DX See Fig. 9.4 on page 295

9.3.1 Memory/IO Interface Memory/IO Interface Address Bus A31 - A2 21:46 9.3.1 Memory/IO Interface Memory/IO Interface Address Bus A31 - A2 Real address mode : only use 18 lines (A19 - A2) Protected mode : use 32 lines A0 - A1 : byte enable output I/O address space : 64 K bytes A2 through A15 and the 3 , 2 1 BE and 3 , 2 1 BE and

21:46 Signals of the 80386DX Fig. 9.4 p295

9.3.1 Memory/IO Interface Data Bus: D31 - D0 Ex 9.2 Ex 9.3 21:46 9.3.1 Memory/IO Interface Data Bus: D31 - D0 Bi-directional Bus Dynamic Bus size : BS16 input BE0 : D7 – D0 BE1 : D15 – D8 BE2 : D23 – D16 BE3 : D31 – D24 Ex 9.2 Ex 9.3

21:46 9.3.1 Memory/IO Interface Fig 9.6 数据复制

9.3.1 Memory/IO Interface BE0#, BE1#, BE2#, BE3# 21:46 80386 DX Memory A31-A2 BE3 BE2 BE1 BE0 80386 DX A31-A2 Memory 0A EB AA 55 7C 06 83 C2 00000000 00000004 BE0-BE3 D31-D0 D31 D0 指令 A31-A2 BE3-BE0 有效数据字节 MOV EAX,[00000004] 00000000 00000000 00000000 000001 0000 7C0683C2 MOV AL, [00000005] 1101 MOV AX, [00000006] 0011 MOV EAX,[00000003] ; EAX=0683C20Ah 00000000 00000000 00000000 000000 0111 1000 0AEBAA55

9.3.1 Memory/IO Interface BS16# 21:46 80386 DX Memory A31-A2 BE3 BE2 BE1 BE0 A31-A2 80386 DX Memory AA 55 0A EB 83 C2 7C 06 00000000 BE0-BE3 00000004 BS16 = 0 D31-D0 D15 D0 指令 A31-A2 BE3-BE0 有效数据字节 MOV [00000004],EAX 00000000 00000000 00000000 000001 0000 0011 7C0683C2 7C067C06 MOV [00000004],AL 1110 XXXXXXC2 MOV [00000007],AL 0111 MOV [00000000],AX 00000000 00000000 00000000 000000 1100 XXXXAA55 MOV [00000002],AX EB0AEB0A MOV [00000005],(E)AX ???? ????????

9.3.1 Memory/IO Interface Memory/IO Interface Ex 9.4 21:46 9.3.1 Memory/IO Interface Memory/IO Interface Address Bus A31 - A2 Real address mode : only use 20 lines (A19 - A2) Protected mode : use 32 lines (A31 - A2) A0 - A1 : byte enable output I/O address space : 64 K bytes A2 through A35 and the Ex 9.4 3 , 2 1 BE and 3 , 2 1 BE and

9.3.1 Memory/IO Interface Memory I/O Control Ex 9.5 21:46 9.3.1 Memory/IO Interface Memory I/O Control M/IO : memory/ input-output indication W/R : write/read indication D/C : data/control indication Ex 9.5 M/IO D/C W/R Type of Bus Cycle 1 Interrupt Acknowledge Idle I/O data read I/O data write Memory code read Halt/shutdown Memory data read Memory data write

9.3.1 Memory/IO Interface Bus Cycle Control Signals 21:46 9.3.1 Memory/IO Interface Bus Cycle Control Signals ADS (Address status) indicates that M/IO, D/C, W/R, BE, and ADDR are all stable READY (Transfer Acknowledge) NA (Next address) Bus Interface control LOCK (Bus lock indication)

9.3.2 Interrupt Interface Interrupt Interface INTR (Interrupt request) 21:46 9.3.2 Interrupt Interface Interrupt Interface INTR (Interrupt request) NMI (Non-maskable Interrupt) RESET (System reset)

9.3.3 DMA Interface DMA Interface HOLD (Bus hold request) 21:46 9.3.3 DMA Interface DMA Interface HOLD (Bus hold request) HLDA (Bus hold acknowledge)

9.3.4 Coprocessor Interface 21:46 9.3.4 Coprocessor Interface Coprocessor Interface PEREQ (Coprocessor request) BUSY (Coprocessor busy) ERROR (Coprocessor error)

21:46 9.4 System Clock

9.4 System Clock System Clock CLK2 : Clock input 21:46 9.4 System Clock System Clock CLK2 : Clock input twice the frequency of the microprocessor : 32MHz(16MHz), 66MHz (33MHz) CLK2 provides the fundamental timing for the Intel386 DX. It is divided by two internally to generate the internal processor clock used for instruction execution. The internal clock is comprised of two phases, ``phase one'' and ``phase two.'' Each CLK2 period is a phase of the internal clock.

15ns = 66.67MHz Max Freq: 33MHz 62.5ns = 16MHz Min Freq: 8MHz 21:46 15ns = 66.67MHz Max Freq: 33MHz 62.5ns = 16MHz Min Freq: 8MHz 不符合要求的时钟输入：

9.5 Bus Cycles Bus State and Bus Cycle 21:46 9.5 Bus Cycles Bus State and Bus Cycle Bus cycle: minimum two processor clock periods (two bus states: T states) - T1 and T2 T state: a processor clock period (twice the period of the CLK2) Non-pipelined and Pipelined Bus Cycle

9.5.1 Non-pipelined Bus Cycle 21:46 9.5.1 Non-pipelined Bus Cycle Non-pipelined Bus Cycle Two T states(T1 and T2)

21:46 9.5.2 Pipelined Bus Cycle Pipelined Bus Cycle

21:46 9.5.3 Idle State Fig 9.12

21:46 9.5.4 Wait States Fig 9.13

21:46 Bus State

21:46

9.6 READ and WRITE Bus Cycle Timing 21:46 9.6 READ and WRITE Bus Cycle Timing Bus Cycles read from memory space locked read from memory space write to memory space locked write to memory space read from I/O space write to I/O space interrupt acknowledge indicate halt or indicate shutdown Non-pipelined Read Cycle Timing Non-pipelined Write Cycle Timing Pipelined Read- and Write-cycle timing

9.6.1 Non-pipelined Read Cycle Timing 21:46 9.6.1 Non-pipelined Read Cycle Timing M/IO D/C W/R Type of Bus Cycle 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 Interrupt Acknowledge Idle I/O data read I/O data write Memory code read Halt/shutdown Memory data read Memory data write

9.6.2 Non-pipelined Write Cycle Timing 21:46 9.6.2 Non-pipelined Write Cycle Timing M/IO D/C W/R Type of Bus Cycle 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 Interrupt Acknowledge Idle I/O data read I/O data write Memory code read Halt/shutdown Memory data read Memory data write

9.6.3 Wait States of Non-pipelined Cycle 21:46 9.6.3 Wait States of Non-pipelined Cycle Ex 9.6

9.6.4 Pipelined Read- and Write-cycle timing 21:46 9.6.4 Pipelined Read- and Write-cycle timing

9.7 Hardware Organization of the Memory Address Space 21:46 9.7 Hardware Organization of the Memory Address Space Physical Memory space : 4GB SW Viewpoint: organized ad individual byte over the address range form 00000000H through FFFFFFFFH HW Organization: No Alignment

21:46 Memory Access

21:46 Memory Access

Memory Access 21:46 为什么Word5,Word1是aligned words?

21:46 Memory Access

9.8 Memory Interface Circuitry 21:46 9.8 Memory Interface Circuitry Memory interface block diagram See Fig 9.25 on page 311 Address latches and buffers ALE (Address Latch Enable) enable-to-output propagation delay(ex: 74F373: 13 ns) 74F373, 74F374 : See Fig 9.26, Fig 9.27, Fig 9.28 Buffering effect : 386 address lines can sink only 4 mA F373 latch can sink a maximum of 24 mA

Memory interface block diagram 21:46 Memory interface block diagram

21:46 9.8.1 Address latches and buffers 74F373 (Octal D-type Latches with 3-state output)

21:46 74F373 Data Sheet

21:46

21:46 74F373 Data Sheet

74F374 (Octal D-type Flip-Flops with 3-state output) 21:46 74F374 (Octal D-type Flip-Flops with 3-state output)

9.8.2 Data Bus Transceivers Data Bus Transceivers 21:46 9.8.2 Data Bus Transceivers Data Bus Transceivers DT/R (data transmit/receive) ; DEN (data bus enable) 74F245 : See Fig 9.30, Fig 9.31 propagation delay : 7 ~ 8 ns Buffering Effect: 386 data lines : 4mA F245 : 64 mA

21:46

21:46

9.8.3 Address Decoders Address Decoders Bus Control logic 21:46 9.8.3 Address Decoders Address Decoders 74F139 dual 2-line-to-4-line decoder 74F138 single 3-line-to-8-line decoder Bus Control logic System Controller PLAs, GALs, and EPLDs PALs : bipolar technology - burning out fuse links GALs : CMOS technology - electrically erasable read-only memory (EEROM) EPLDs : CMOS technology - electrically programmable read only memory (EPROM)

每片存储容量: 228 (256MB)字节(A29-A2), 共16片. 21:46 Fig 9.34 2-4译码 Fig 9.36 电路。 232 = 22 *228 *22 A31-A30 A29-A2 A1-A0 每片存储容量: 228 (256MB)字节(A29-A2), 共16片. 片选信号: SCEi = BELi/4 OR CEi mod 4 (i=0,1,..,15) 是否必须要使用A31-A30来译码? 若每片存储容量为227 (128MB)字节? Fig 9.37. 3-8译码 1-2译码? A29-A2 D31-D24 或D23-D16 SCEi

21:46 Fig 9.33(a) & (b)

9.9 Input/Output Isolated Input/Output 21:46 9.9 Input/Output Isolated Input/Output Isolated I/O space : See Fig 9.47 page 0 : 0-255 ; direct access Advantages Full memory space Special Instructions - maximize I/O performance Disadvantages Restricted Instruction Power Separate I/O control signals

9.9.2 Memory Mapped Input/Output 21:46 9.9.2 Memory Mapped Input/Output Memory mapped I/O Advantages Powerful Instruction set No I/O control signals Disadvantages Part of Memory space is lost the memory instructions tend to execute slower than those specially designed for isolated I/O

9.10 The Isolated I/O Interface 21:46 9.10 The Isolated I/O Interface Fig 9.41

The Isolated I/O Interface 21:46 The Isolated I/O Interface Fig 9.43

21:46 9.11 I/O Bus Cycles Fig 9.44

21:46 9.12 I/O Instructions Fig 9.45

21:46 谢谢大家

Memory Devices and Subsystem Design 21:46 Memory Devices and Subsystem Design Memory Subsystem Design Read-only Memory Random access read/write memories FLASH memory Wait-state Circuitry Cache memory Cache controller Read-Only Memory ROM, PROM, EPROM ROM BIOS(Basic Input/Output System) Read Operation : See Fig 10.4 Standard EPROM ICs : See Fig 10.6, 10.7, 10.9

21:46 Read-Only Memory

21:46

21:46 27C256 ROM Data Sheet

21:46

21:46 27C256 ROM Data Sheet

RAM Random Access Read/Write Memories Static and Dynamic RAMs 21:46 RAM Random Access Read/Write Memories Static and Dynamic RAMs SRAM DRAM : refreshing Static RAM Block Diagram and Standard SRAM ICs : See Fig 10.11, 10.12, 10.13, 10.16 Read/Write Operation : See Fig 10.17, 10.18

Block Diagram and Standard SRAM ICs 21:46 Block Diagram and Standard SRAM ICs

21:46

21:46 Standard SRAM ICs

Read/Write-Cycle Timing 21:46 Read/Write-Cycle Timing

21:46

Dynamic RAM Dynamic RAM 21:46 Dynamic RAM Dynamic RAM Standard DRAM ICs : See Fig 10.19, 10.20, 10.21 Block Diagram of DRAM : See Fig 10.21, 10.22 Read/Write Operation

21:46 Block Diagram of DRAM

21:46

Read/Write-Cycle Timing 21:46 Read/Write-Cycle Timing

Reading Assignment Read Chapter 10 Flash Memory Cache Memory 21:46 Reading Assignment Read Chapter 10 Flash Memory Cache Memory Cache Controller