EE115C – Winter 2009 Digital Electronic Circuits Presentation Template

Low-Power 10-bit Adder Design Name 1 Name 2

Design Summary A) Adder topology, B) Circuit Style (e.g. CSA, static CMOS) C) WHY: about A, about D, other (e.g. moderate A, fast, regular design) Note: E = average energy reported by simulating the testbench Schematic Layout Verfication VDD = 1V tp = 2ns tp = [] ns DRC: Y / N tp= [] ns VDD = [] V Same VDD LVS: Y / N E = [] pJ A = [] mm2 Func: Y / N *Replace [] with your numbers: e.g. tp = 0.65ns etc. EE115C – Winter 2009

Critical Path Analysis Highlight critical path block diagram of design / crit-path delay equation SAMPLE EE115C – Winter 2009

SAMPLE Design Optimization gate level critical path MOS detail of gates & sizing strategy 0.96 P0 0.96 P1 0.96 P6 0.96 T-Gate 1.44 1.44 1.44 S7 Ci P7 0.96 SAMPLE G0 G1 G6 0.96/ 0.48 3.84/ 1.92 0.48 0.48 0.48 CLKB 0.48 Propagate Carry instead of Carry to reduce transistor count along Manchester chain NMOS only pass gate as all Carry nodes are pre-charged to VDD at CLK=0 Dynamic logic in Ci inverter and G0:7 AND gates  footless Domino in Manchester chain Generate CO and Sum to incorporate the 4X buffer in signal chain. EE115C – Winter 2009

SAMPLE Functionality Check Screenshot of relevant waveforms EE115C – Winter 2009

SAMPLE Adder Layout Highlight critical path Indicate size FA0 FA1 FA2 INPUT BUFFER INPUT BUFFER 3 Indicate size FA0 FA1 FA2 FA3 y = 38.3mm SAMPLE x = 33.0mm OUTPUT BUFFER OUTPUT BUFFER 1 CLOCK CHAIN Show layout 4 OUTPUT BUFFER OUTPUT BUFFER Area, AR Area: 1264mm2 Aspect ratio: 1.16 FA7 FA6 FA5 FA4 (6) Anything else Density: 85% INPUT BUFFER INPUT BUFFER 5 EE115C – Winter 2009

Discussion Three most important features of your design (e.g. It meets the timing spec, so energy is minimized) (e.g. Highly regular layout design made easy to route) (e.g. Mirror adder for reduced area) Given another chance, 3 things you would do different (e.g. Change topology, because…) (e.g. Optimize only last few stages to save design time) (e.g. Nothing, I nailed it down! ;)) Exactly these 6 slides, not a slide more, not a slide less EE115C – Winter 2009