32 BIT PARALLEL LOAD REGISTER WITH CLOCK GATING

Slides:

Advertisements

Similar presentations

Course: Low power design of electronic circuits Student: Ahmed Faraz.

Advertisements

Feb. 17, 2011 Midterm overview Real life examples of built chips

Keeping Hot Chips Cool Ruchir Puri, Leon Stok, Subhrajit Bhattacharya IBM T.J. Watson Research Center Yorktown Heights, NY Circuits R-US.

Synchronous Digital Design Methodology and Guidelines

Dynamic SCAN Clock control In BIST Circuits

Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.

Low Voltage Sequential Circuit With a Ring Oscillator Clock ELEC 6270 Low power design of Electronic Circuits Spring, 2009 Presented by Mridula Allani.

4/28/05Vemula: ELEC72501 Enhanced Scan Based Flip-Flop for Delay Testing By Sudheer Vemula.

CS 300 – Lecture 3 Intro to Computer Architecture / Assembly Language Sequential Circuits.

REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy.

Dec. 6, 2005ELEC Glitch Power1 Low power design: Insert delays to eliminate glitches Yijing Chen Dec.6, 2005 Auburn university.

Low Power Implementation of Scan Flip-Flops Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

8/19/04ELEC / ELEC / Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Fall 2004 Vishwani.

Priyadharshini Shanmugasundaram Vishwani D. Agrawal DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING.

EE166 Final Presentation Patsapol Kriausakul Sung Min Park Dennis Won Howard Yuan.

8/18/05ELEC / Lecture 11 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

11/29/2007ELEC Class Project Presentation1 LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS Mohammed Ashfaq Shukoor ECE Department.

1 32-bit parallel load register with clock gating ECE Department, 200 Broun Hall, Auburn University, Auburn, AL 36849, USA Lan Luo ELEC.

ENGIN112 L26: Shift Registers November 3, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 26 Shift Registers.

Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:

Low power architecture and HDL coding practices for on-board hardware applications Kaushal D. Buch ASIC Engineer, eInfochips Ltd., Ahmedabad, India

KU College of Engineering Elec 204: Digital Systems Design

Unit 12 Registers and Counters Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.

ECE 331 – Digital System Design Power Dissipation and Additional Design Constraints (Lecture #14) The slides included herein were taken from the materials.

USING SAT-BASED CRAIG INTERPOLATION TO ENLARGE CLOCK GATING FUNCTIONS Ting-Hao Lin, Chung-Yang (Ric) Huang Graduate Institute of Electrical Engineering,

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

CS3350B Computer Architecture Winter 2015 Lecture 5.2: State Circuits: Circuits that Remember Marc Moreno Maza [Adapted.

ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi.

1 VLSI Design SMD154 LOW-POWER DESIGN Magnus Eriksson & Simon Olsson.

Power Reduction for FPGA using Multiple Vdd/Vth

Low Power Architecture and Implementation of Multicore Design Khushboo Sheth, Kyungseok Kim Fan Wang, Siddharth Dantu ELEC6270 Low Power Design of Electronic.

1 Sign Bit Reduction Encoding for Low Power Applications Hsin-Wei Lin Saneei, M. Afzali-Kusha, A. and Navabi, Z. Sign Bit Reduction Encoding for Low Power.

Low-Power Multipliers with Data Wordlength Reduction Kyungtae Han Brian L. Evans Earl E. Swartzlander, Jr.

Design for Testability By Dr. Amin Danial Asham. References An Introduction to Logic Circuit Testing.

EKT 221/4 DIGITAL ELECTRONICS II  Registers, Micro-operations and Implementations - Part3.

Radix-2 2 Based Low Power Reconfigurable FFT Processor Presented by Cheng-Chien Wu, Master Student of CSIE,CCU 1 Author: Gin-Der Wu and Yi-Ming Liu Department.

By Praveen Venkataramani

Abdullah Said Alkalbani University of Buraimi

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-Graduate Project Improving Timing, Area, and Power Speaker: 黃乃珊 Adviser: Prof.

Jun Seomun, Insup Shin, Youngsoo Shin Dept. of Electrical Engineering, KAIST DAC’ 10.

DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register

1 Energy-Efficient Register Access Jessica H. Tseng and Krste Asanović MIT Laboratory for Computer Science, Cambridge, MA 02139, USA SBCCI2000.

Kautalya Mishra. MULTI-CYCLE DATAPATH CLOCK CTR Unnecessary power is consumed by components that are not currently in use in an instruction cycle. This.

Uniformly-switching Logic for Cryptographic Hardware D. Maslov - University of Victoria, Canada I. L. Markov - University of Michigan, USA.

16 Bit Logarithmic Converter Tinghao Liang and Sara Nadeau.

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dr. Shi Dept. of Electrical and Computer Engineering.

RTL Hardware Design by P. Chu Chapter 9 – ECE420 (CSUN) Mirzaei 1 Sequential Circuit Design: Practice Shahnam Mirzaei, PhD Spring 2016 California State.

LOW POWER DESIGN METHODS

Dr. Clincy Professor of CS

Computer Organization

LOW POWER DESIGN METHODS V.ANANDI ASST.PROF,E&C MSRIT,BANGALORE.

SECTIONS 1-7 By Astha Chawla

Digital Decode & Correction Logic

Very low voltage 16-bit counter in high leakage static CMOS technology

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS Chao Han ELEC 6270.

DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register

Reading: Hambley Ch. 7; Rabaey et al. Sec. 5.2

Counters and Registers

Elec 2607 Digital Switching Circuits

ELEC 6970: Low Power Design Class Project By: Sachin Dhingra

FPGA Glitch Power Analysis and Reduction

Power Reduction Technique

University of Texas at Austin

Reading: Hambley Ch. 7; Rabaey et al. Secs. 5.2, 5.5, 6.2.1

Low Power Digital Design

Measuring the Gap between FPGAs and ASICs

Outline Registers Counters 5/11/2019.

Reference Chapter 7 Moris Mano 4th Edition

Presentation transcript:

32 BIT PARALLEL LOAD REGISTER WITH CLOCK GATING PRARDIVA MANGILIPALLY ELEC 6270

OUTLINE: Objective Basic idea Basic gating circuit Modified clock gating circuit Design platform Results Conclusion

OBJECTIVE: To measure the average power for a 32 bit parallel load register with and without clock gating. To compare the results for the same. To study the effect of clock gating on power consumption for a 32 bit parallel load register.

CLOCK GATING: Clock gating is one of the power saving techniques in which additional logic is added to a circuit to prune the clock tree ,thus disabling portions of circuitry so that flipflops do not change state.As a result switching power goes to zero.

MODIFIED CLOCK GATING CIRCUIT:

Design platform: Latchfree clock gating circuit Tools used: Modelsim, leonardo, Design Architect, Eldo Technology: tsmc018 Clock frequency: 50MHz Operating voltage: 1.8V

Pattern:0000000 Without clock gating Average power: = 242.6818U W With clock gating Average power: 42.8374U W

Pattern:111111111 Without clock gating With clock gating Average power: 244.0567UW With clock gating Average power: 27.4138UW

Pattern:101010 Without clockgating Average power:457.2622uW With clock gating Average power: 628.8430U W

PATTERN:10111011 WITH CLOCK GATING AVERAGE POWER:337.1065UW WITHOUT CLOCKGATING: AVERAGE POWER:357.8213UW WITH CLOCK GATING AVERAGE POWER:337.1065UW

PATTERN:01000100 WITH CLOCKGATING AVERAGE POWER:331.2031UW WITHOUT CLOCKGATING AVERAGE POWER:355.11064UW WITH CLOCKGATING AVERAGE POWER:331.2031UW

PATTERN:11011101 WITHOUT CLOCKGATING: AVERAGE POWER:352.7703UW WITH CLOCKGATING: AVERAGE POWER:324.1347UW

PATTERN:00100010 WITHOUT CLOCKGATING AVERAGE POWER:344.7696UW WITH CLOCKGATING AVERAGE POWER:337.4078UW

INPUT12:00000010100000010101000000000000000000000000000000 WITHOUT CLOCK GATING: AVERAGE POWER:288.4402UW WITH CLOCK GATING: AVERAGE POWER:165.1852UW

INPUT12: 11111111101010111111010111111111111111111111111111 WITHOUT CLOCKGATING: AVERAGE POWER:289.1212UW WITH CLOCKGATING: AVERAGE POWER:146.8568UW

Power Reductions: Without clock gating With clock gating TRANSITION DENSITY EXPECTED POWER (UW) OBSERVED POWER POWER REDUCTION (%) 0.0000 244.0512 244.0567 68.7008 27.4138 88.77 0.0004 242.6944 242.6818 70.1134 42.8374 82.35 0.1000 262.4961 289.1212 182.0272 146.8568 49.21 0.1024 289.1168 288.4402 170.3126 165.1852 42.73 0.2500 357.7568 357.8213 340.1931 337.1065 5.51 0.5000 457.1456 457.2622 655.6832 628.840 -37.5

CONCLUSIONS: Clock gating technique effectively reduces dynamic power in most of the cases. However,it increases power when there are transitions in every clock cycle.This increase is due to the extra power consumed by the ex-nor and nor gates in the clock gating circuit which account to about 58% increase in total hardware. If this increase in hardware could be reduced then the power savings can be increased even in the worst case which calls for the implementation of a different clock gating circuit or the usage of low power ex-or’s discussed in the class.

REFERENCES: Class lecture slides at http://www.eng.auburn.edu/~vagrawal/ COURSE/ E6270_Spr09/course.html Frank Emnett and Mark Biegel, Power Reduction Through RTL Clock Gating, SNUG2000(This paper discusses a method to avoid premature truncation of the clock).

THANK YOU