Last Lecture Current Mirrors → Chp. #4 Current Mirror Design Problems 2/22/2019 Last Lecture Current Mirrors → Chp. #4 Current Mirror Design Problems Homework #1 & #2 Analog Circuit Design

2/22/2019 Homework #2 → Revisited! Design the cascode current mirror for the following specifications: Iout = 2·Iin=[0-10] µA Vout(min) < 0.5V Vin < 0.9V Ibias VDD M2 M1 Iout M4 M3 Iin Vout + _ M2=2·M1 Vout(min)=Vds1(sat)+Vds2(sat) = 0.5V Choose Vds1(sat)=Vds2(sat)=0.25V Find W/L for M4,M2, and M1 Vin(max)=Vgs1=Vton+Vds1(sat)=0.95V does not satisfy Vds1(sat)=0.2V in order to satisfy Find new W/L for M1 and M2 Vgs3=Vgs4+Vds2(sat) Vds3(sat)=Vds4(sat)+Vds2(sat)=0.45V Find W/L for M3 Analog Circuit Design

? Current References → Revisited! 2/22/2019 Current References → Revisited! Iref VDD M2 M1 Iout An independent current source that has a high degree of precision and stability ? Important Concepts: Sensitivity: All Circuits Have Performance That Varies As The Values Of The Components Change – Temperature – Time (Aging) – Phase Of The Moon – Component Tolerance In Manufacturing – Etc Temperature Coefficient: Ideally a current reference should be independent of: power supply temperature noise process variations Analog Circuit Design

? Simple Current Reference Process and Temperature Dependant 2/22/2019 Simple Current Reference VDD Process and Temperature Dependant TCVton - negative ± 10% Vto variation ? Iref Iout= R Linear dependence on VDD Q1 Q2 AE1=AE2 Process and Temperature Dependant ±TCR (depends on material) ± 30% R variation Analog Circuit Design

An Improved Current Reference 2/22/2019 An Improved Current Reference Iref VDD M2 M1 Iout R1 R2 Iout= TCIout= Output current is no longer sensitive to Vdd … to some degree! BJTs in a MOS process? Temperature Coefficient of VBE Temperature Coefficient of R2 Analog Circuit Design

Bipolar Transistors in CMOS n-well Process 2/22/2019 Bipolar Transistors in CMOS n-well Process vertical parasitic BJT lateral parasitic BJT Analog Circuit Design

An Supply Independent Current Reference 2/22/2019 An Supply Independent Current Reference Assume: AE2= N∙AE1 M2= M1 M3= M4 VDD M1 Iref R1 M3 M4 M2 Vp Q1 Q2 I1=Iref/N TCIout=TCBJT-TCR-TCCMOS + VSG - Threshold Voltage has a positive dependence on temperature R(T) = R(T0) • [1 + TCRl (T- T0) + TCR2 (T-R2 (T- T)2] vertical bjts Analog Circuit Design

An Supply Independent Current Reference → CMOS! 2/22/2019 An Supply Independent Current Reference → CMOS! Assume: M2= N∙ M1 M3= M4 VDD M1 Iref R1 M3 M4 M2 Vp Iout=Iref=N IM1 TCIout= TCR + TCCMOS Where IDO= current at  VGS=VTH Saturation Sub-Vth Analog Circuit Design

Current Reference → Higher Supply Regulation! 2/22/2019 Current Reference → Higher Supply Regulation! Assume: M2= N∙ M1 M3= M4 Iout= TCIout= VDD M1 Iref R1 M3 M4 M2 Vp Sub-Vth Analog Circuit Design

Linear TC Cancellation 2/22/2019 Linear TC Cancellation VDD M1 R1 M3 M4 M2 R2 M5 M6 M7 M8 M9 M11 M10 Assume: M2= N∙ M1 M3= M4 Analog Circuit Design