ESE534 Computer Organization Day 6: February 1, 2012 Energy, Power, Reliability Penn ESE534 Spring2012 -- Mehta & DeHon

Today Energy tradeoffs Voltage limits and leakage Variations Penn ESE534 Spring2012 -- Mehta & DeHon

At Issue Many now argue energy will be the ultimate scaling limit (not lithography, costs, …) Proliferation of portable and handheld devices …battery size and life biggest issues Cooling, energy costs may dominate cost of electronics Even server room applications Penn ESE534 Spring2012 -- Mehta & DeHon

Preclass 1 1GHz case 2GHz case Voltage? Energy per Operation? Power required for 2 processors? 2GHz case Power required for 1 processor? Penn ESE534 Spring2012 -- Mehta & DeHon

tgd=Q/I=(CV)/I Id,sat=(mCOX/2)(W/L)(Vgs-VTH)2 Energy and Delay Penn ESE534 Spring2012 -- Mehta & DeHon

Energy/Delay Tradeoff EV2 tgd1/V We can trade speed for energy E×(tgd)2 constant ¿gd=(CV)/I Id,sat (Vgs-VTH)2 Martin et al. Power-Aware Computing, Kluwer 2001 http://caltechcstr.library.caltech.edu/308/ Penn ESE534 Spring2012 -- Mehta & DeHon

Area/Time Tradeoff Also have Area-Time tradeoffs HW2 spatial vs temporal multipliers See more next week Compensate slowdown with additional parallelism …trade Area for Energy  Architectural Option Penn ESE534 Spring2012 -- Mehta & DeHon

Question By how much can we reduce energy? What limits us? Penn ESE534 Spring2012 -- Mehta & DeHon

Challenge: Power Penn ESE534 Spring2012 -- Mehta & DeHon

Origin of Power Challenge Limited capacity to remove heat ~100W/cm2 force air 1-10W/cm2 ambient Transistors per chip grow at Moore’s Law rate = (1/F)2 Energy/transistor must decrease at this rate to keep constant power density P/tr  CV2f E/tr  CV2 …but V scaling more slowly than F Penn ESE534 Spring2012 -- Mehta & DeHon

Energy per Operation Ctotal = # transistors × Ctr Ctr scales (down) as F # transistors scales as F-2 …ok if V scales as F… Penn ESE534 Spring2012 -- Mehta & DeHon

ITRS Vdd Scaling: More slowly than F Penn ESE534 Spring2012 -- Mehta & DeHon

ITRS CV2 Scaling: More slowly than (1/F)2 Penn ESE534 Spring2012 -- Mehta & DeHon

Origin of Power Challenge Transistors per chip grow at Moore’s Law rate = (1/F)2 Energy/transistor must decrease at this rate to keep constant E/tr  CV2 Penn ESE534 Spring2012 -- Mehta & DeHon

Historical Power Scaling [Horowitz et al. / IEDM 2005] Penn ESE534 Spring2012 -- Mehta & DeHon

Microprocessor Power Density Watts The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE534 Spring2012 -- Mehta & DeHon http://www.nap.edu/catalog.php?record_id=12980

Intel Power Density Penn ESE534 Spring2012 -- Mehta & DeHon

Impact Power Limits Integration Source: Carter/Intel 18 Penn ESE534 Spring2012 -- Mehta & DeHon

Impact Power density is limiting scaling Can already place more transistors on a chip than we can afford to turn on! Power is potential challenge/limiter for all future chips. Only turn on small percentage of transistors? Operate those transistors as much slower frequency? Find a way to drop Vdd? Penn ESE534 Spring2012 -- Mehta & DeHon

How far can we reduce Vdd? Penn ESE534 Spring2012 -- Mehta & DeHon

Limits Ability to turn off the transistor Parameter Variations Noise (not covered today) Penn ESE534 Spring2012 -- Mehta & DeHon

MOSFET Conduction From: http://en.wikipedia.org/wiki/File:IvsV_mosfet.png Penn ESE534 Spring2012 -- Mehta & DeHon

Transistor Conduction Three regions Subthreshold (Vgs<VTH) Linear (Vgs>VTH) and (Vds < (Vgs-VTH)) Saturation (Vgs>VTH) and (Vds > (Vgs-VTH)) Penn ESE534 Spring2012 -- Mehta & DeHon

Ids,sat=(mCOX/2)(W/L)(Vgs-VTH)2 Saturation Region (Vgs>VTH) (Vds > (Vgs-VTH)) Ids,sat=(mCOX/2)(W/L)(Vgs-VTH)2 Penn ESE534 Spring2012 -- Mehta & DeHon

Linear Region Ids,lin=(mCOX)(W/L)((Vgs-VTH)Vds-(Vds)2/2) (Vgs>VTH) Penn ESE534 Spring2012 -- Mehta & DeHon

Subthreshold Region (Vgs<VTH) [Frank, IBM J. R&D v46n2/3p235] Penn ESE534 Spring2012 -- Mehta & DeHon

Operating a Transistor Concerned about Ion and Ioff Ion drive (saturation) current for charging Determines speed: Tgd = CV/I Ioff leakage current Determines leakage power/energy: Pleak = V×Ileak Eleak = V×Ileak×Tcycle Penn ESE534 Spring2012 -- Mehta & DeHon

Leakage To avoid leakage want Ioff very small Switch V from Vdd to 0 Vgs in off state is 0 (Vgs<VTH) Penn ESE534 Spring2012 -- Mehta & DeHon

Leakage Leakage limits VTH in turn limits Vdd S90mV for single gate S70mV for double gate For lowest leakage, want S small, VTH large 4 orders of magnitude IVT/IoffVTH>280mV Leakage limits VTH in turn limits Vdd Penn ESE534 Spring2012 -- Mehta & DeHon

Id,sat=(mCOX/2)(W/L)(Vgs-VTH)2 How maximize Ion/Ioff ? Maximize Ion/Ioff – for given Vdd ? EswCV2 Get to pick VTH, Vdd Id,sat=(mCOX/2)(W/L)(Vgs-VTH)2 Id,lin=(mCOX)(W/L)(Vgs-VTH)Vds-(Vds)2/2 Penn ESE534 Spring2012 -- Mehta & DeHon

Preclass 2 E = Esw + Eleak Eleak = V×Ileak×Tcycle EswCV2 Ichip-leak = Ndevices ×Itr-leak Penn ESE534 Spring2012 -- Mehta & DeHon

Preclass 2 Eleak(V) ? Tcycle(V)? Penn ESE534 Spring2012 -- Mehta & DeHon

In Class Assign calculations Collect results on board SIMD – each student computes for a different Voltage Collect results on board Should go quick once students have time to calculate Identify minimum energy point and discuss Penn ESE534 Spring2012 -- Mehta & DeHon

Graph for In Class Penn ESE534 Spring2012 -- Mehta & DeHon

Impact Subthreshold slope prevents us from scaling voltage down arbitrarily. Induces a minimum operating energy. Penn ESE534 Spring2012 -- Mehta & DeHon

Challenge: Variation Penn ESE534 Spring2012 -- Mehta & DeHon

Statistical Dopant Count and Placement [Bernstein et al, IBM JRD 2006] Penn ESE534 Spring2012 -- Mehta & DeHon

Vth Variability @ 65nm [Bernstein et al, IBM JRD 2006] Penn ESE534 Spring2012 -- Mehta & DeHon

(From ITRS prediction) Variation Fewer dopants, atoms  increasing Variation How do we deal with variation? % variation in VTH (From ITRS prediction) 40 Penn ESE534 Spring2012 -- Mehta & DeHon 40

Impact of Variation? Higher VTH? Lower VTH? Not drive as strongly  slower Id,sat (Vgs-VTH)2 Lower VTH? Not turn off as well  leaks more Penn ESE534 Spring2012 -- Mehta & DeHon

Variation Ion,min=Ion(Vth,max) Margin for expected variation Must assume VTH can be any value in range Ion,min=Ion(Vth,max) Id,sat (Vgs-VTH)2 Vgs = Vdd Probability Distribution VTH Penn ESE534 Spring2012 -- Mehta & DeHon

Margining Ion,min=Ion(Vth,max) Must raise Vdd to increase drive strength Increase energy Ion,min=Ion(Vth,max) Id,sat (Vgs-VTH)2 Vgs = Vdd Probability Distribution VTH Penn ESE534 Spring2012 -- Mehta & DeHon

Variation Increasing variation forces higher voltages On top of our leakage limits 44 Penn ESE534 Spring2012 -- Mehta & DeHon 44

Variations Margins growing due to increasing variation Probability Distribution Delay New Old Margins growing due to increasing variation Margined value may be worse than older technology? One key issue showing up today is increased variation. (We noted on slide 2 that decreasing number of dopants directly leads to increased variance in device characterstics.) As the variation increases, so must our margins. This diminishes the benefit we see from advanced technology. The diagram shows that the mean device behavior for a smaller feature size technology gets better (i.e. lower delay) as expected. This is what we’re tracking on the ideal (black) curve. However, the variance for the advanced (smaller feature size) technology is larger. This means that after we apply margining for yield and worst-case path effects, the chip-level benefit is lower. …and so, the larger variance means we do not see the full, ideal scaling in device performance (hence the purple curve). For DoD system, we often require greater margins to accommodate wider operating scenarios and/or as part of derating for harsh environment operation. This greater margining leads to even a greater degradation of performance. In the extreme, this might lead to inversion where the new technology, with margining, is actually worse than the older technology with lower variation. In practice, it’s unlikely that this inversion will arise entirely based on this effect alone, but this effect is composed with the earlier effects of defect and fault mitigation and the composite effect can likely lead to this inversion. The solution here is to go away from worst-case margined designs. With the methodologies proposed here, we make the designs tolerant to failures-in-the-middle. That allows us to detect the uncommon cases where the device fails to meet timing and recover. This allows us to achieve performance on the red curve. Penn ESE534 Spring2012 -- Mehta & DeHon

End of Energy Scaling? Black nominal Grey with variation [Bol et al., IEEE TR VLSI Sys 17(10):1508—1519] Penn ESE534 Spring2012 -- Mehta & DeHon

Chips Growing Larger chips (billions of transistors)  sample further out on distribution curve From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg Penn ESE534 Spring2012 -- Mehta & DeHon

Admin Homework due Monday Reading for Monday on web Section 3.5 has changed Please grab updated copy Reading for Monday on web André back on Monday Penn ESE534 Spring2012 -- Mehta & DeHon

Big Ideas Continued scaling demands Can trade time for energy … area for energy Variation and leakage limit voltage scaling Power major limiter going forward Can put more transistors on a chip than can switch Continued scaling demands Deal with noisier components High variation … other noise sources Penn ESE534 Spring2012 -- Mehta & DeHon