Native FEC simulation for UDP Matthew Brindley 3220777 Elbert Wang 3159861

Problem Statement Internet traffic increasing rapidly Core networks scaled to terabits-per-second and increasing Current routers have the following problems: Delay and jitter, high cost, power consumption and heat dissipation All-optical packet switched routers Examples: IRIS Lasor Difficult to employ integrated optical buffers Challenge: Reliability of packet traffic with near zero buffer in core link. A potential solution: Edge to edge based packet level “Forward Error Correction” (FEC)

Work undertaken Native simulation of UDP data flow under near zero core buffer conditions Dumbbell topology Single core link Multiple edge routers Multiple End-hosts per edge router Forward Error Correction Feedback less Image source: On the Efficacy of Edge-to-Edge Packet-Level FEC in Near-Zero Buffer Core Networks p.4 – Vishwanath, A, Sivaraman, V, Thottan, M, Dovrolis, C

Approach Simulation in C Discretised time Random packet generation at each client Packet generation using random exponential distribution size FEC counter

Limitations Native simulation Granularity Discrete time Adjustable tick per microsecond ‘All-knowing’ loss tracking elements rather than a robust packet sequence checking system

Initial Results

Conclusions Initially with FEC block size increase % loss reduction improves As FEC block size continues to increase, % loss increases The best % loss reduction at FEC block size 3

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