Day 18: October 20, 2010 Ratioed Logic Pass Transistor Logic ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 20, 2010 Ratioed Logic Pass Transistor Logic Penn ESE370 Fall2010 -- DeHon

Today Ratioed Gates Pass Transistor Logic Correctness Performance Power Implications Pass Transistor Logic Muxes Composition Logic Penn ESE370 Fall2010 -- DeHon

Ratioed Logic Idea Maybe only need to build one network Build NFET pulldown Exploit high N mobility Penn ESE370 Fall2010 -- DeHon

Size for R0/2 drive? …and Vol<0.1Vdd Penn ESE370 Fall2010 -- DeHon

Compare Static CMOS Total Transistor Width Input capacitance load Penn ESE370 Fall2010 -- DeHon

Power? Istatic ? Output high? Output low? Ileak Ipmos_on Vdd/(R0/2) -- for our sample case Penn ESE370 Fall2010 -- DeHon

Power Ptot ≈ a(½Cload+Csc)V2f +PlowV2/Rpon +(1-Plow)VI’s(W/L)e-Vt/(nkT/q) Penn ESE370 Fall2010 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2010 -- DeHon

How size for R0/2 drive? Penn ESE370 Fall2010 -- DeHon

Which Implementation is faster in ratioed logic? Penn ESE370 Fall2010 -- DeHon

Illustrates Preferred gate changes Penn ESE370 Fall2010 -- DeHon

How size for R0/2 drive? K-input nor Penn ESE370 Fall2010 -- DeHon

When better than CMOS nor-k? Better = smaller, lower input capacitance Penn ESE370 Fall2010 -- DeHon

Ratioed Logic Tradeoff noise margin for Reduced area? Capacitive load? Dissipates static power in one mode Penn ESE370 Fall2010 -- DeHon

Admin Project: Due Friday Midterm: next Wednesday (one week from today) Penn ESE370 Fall2010 -- DeHon

Pass Transistor Logic Penn ESE370 Fall2010 -- DeHon

What does this do? S A B Penn ESE370 Fall2010 -- DeHon

Behavior What is the equivalent logic function? S A B Penn ESE370 Fall2010 -- DeHon

Size Comparison How does this compare to the static CMOS alternative? transistor count? Penn ESE370 Fall2010 -- DeHon

Delay Assume R0/2 drive 10C0 load What else need to know? 5 2 5 Penn ESE370 Fall2010 -- DeHon

Delay Assume R0/2 drive 10C0 load What else need to know? Cdiff Assume Cdiff≈Cgate 5 2 Penn ESE370 Fall2010 -- DeHon

What’s different? What’s different about the output? Penn ESE370 Fall2010 -- DeHon

Output ok? Is the output usable? Penn ESE370 Fall2010 -- DeHon

CMOS DC Transfer Function Penn ESE370 Fall2010 -- DeHon

After CMOS Inverter Penn ESE370 Fall2010 -- DeHon

What does this do? Penn ESE370 Fall2010 -- DeHon

Cascade Functional? Penn ESE370 Fall2010 -- DeHon

Voltage Drop Voltage drop across any number of series transistors is one Vth Think about two series transistors as one transistor of twice the length Penn ESE370 Fall2010 -- DeHon

Pinch Off Day 9 When voltage drops below VT, drops out of inversion Occurs when: VGS-VDS< VT Conclusion: current cannot increase with VDS once VDS> VGS-VT current must adjust so that VDS= VGS-VT If current dropped to zero, then would invert and conduct again… Penn ESE370 Fall2010 -- DeHon

Performance? Assume R0/2 drive 10C0 load Cdiff=Cgate 5 2 5 Penn ESE370 Fall2010 -- DeHon

What does this do? A B Penn ESE370 Fall2010 -- DeHon

Performance R0/2 drive 10C0 load 5 2 5 Penn ESE370 Fall2010 -- DeHon

Performance R0/2 drive 10C0 load Penn ESE370 Fall2010 -- DeHon

Not Isolating Does not isolate downstream capacitive load Stage delay now dependent on downstream stages Penn ESE370 Fall2010 -- DeHon

Ideas There are other logic disciplines We have the tools to analyze Ratioed Logic Tradeoff noise margin for Reduced area? Capacitive load? Dissipates static power in one mode Pass Transistor Logic Possibly smaller Not rail-to-rail Cascading without buffering  slow Penn ESE370 Fall2010 -- DeHon