SYEN 3330 Digital Systems Chapter 6 – Part 5 SYEN 3330 Digital Systems

Overview of Chapter 6 Types of Sequential Circuits Storage Elements Latches Flip-Flops Sequential Circuit Analysis State Tables State Diagrams Sequential Circuit Design Specification Assignment of State Codes Implementation HDL Representation SYEN 3330 Digital Systems

Sequential Circuit Implementation SYEN 3330 Digital Systems

State Coding – Example 1 How may assignments of codes with a minimum number of bits? 2 – A = 0, B = 1 or A = 1, B = 0 Does it make a difference? Only in variable inversion, so small if any. SYEN 3330 Digital Systems

State Coding – Example 2 How may assignments of codes with a minimum number of bits? 4  3  2  1 = 24 Does code assignment make a difference? See Next Two Slides SYEN 3330 Digital Systems

State Coding – Example 2 Present State Next State x = 0 x = 1 Output 0 0 0 1 1 0 1 1 1 Code 1: A = 0 0, B = 0 1, C = 1 0, D = 1 1 See Next Slide SYEN 3330 Digital Systems

State Coding – Example 2 Present State Next State x = 0 x = 1 Output 0 0 0 1 1 1 1 0 1 Code 2: A = 0 0, B = 0 1, C = 1 1, D = 1 0 So it does make a difference in cost! SYEN 3330 Digital Systems

Implementation Present State Next State x = 0 x = 1 Output 0 0 0 1 1 1 1 1 1 0 1 Using code 2: SYEN 3330 Digital Systems

Implementation with DFF Present State Next State x = 0 x = 1 DFFY1 DFFY2 0 0 0 1 1 1 1 1 0 Using D = Q(t+1): SYEN 3330 Digital Systems

DFF Schematic SYEN 3330 Digital Systems

Implementation with TFF Present State Next State x = 0 x = 1 TFFY1 TFFY2 0 0 0 1 1 1 1 1 0 Using T = Q(t)  Q(t+1) SYEN 3330 Digital Systems

Implementation with JKFF SYEN 3330 Digital Systems

Implementation with JKFF (Cont.) SYEN 3330 Digital Systems

Implementation with JKFF (Cont.) Present State Next State x = 0 x = 1 JY1 KY1 0 0 0 1 X 1 1 1 1 0 SYEN 3330 Digital Systems

RS Flip-Flop Implementation SYEN 3330 Digital Systems

RS Implementation (Cont.) Present State Next State x = 0 x = 1 SY1 RY1 0 0 0 1 X 1 1 1 1 0 SYEN 3330 Digital Systems

Sequential Logic Design Process SYEN 3330 Digital Systems

Second Example – Register File Cell: State Diagram Design Make the state unchanged (Hold Reg) by adding all unused input combinations for each state. CLS,LDS,Data_in State/Data_out(i) 0, 1, 0; 1, -, - 0, 1, 1 RESET A/0 B/1 0,1,0; 1,-,-; 0,0,- 0,1,1; 0,0,- SYEN 3330 Digital Systems

Second Example – Register File Cell: State Table – State Assignment (A=0, B=1) Input: State: 000 001 010 011 100 101 110 111 Output A B 1 Input: State: 000 001 010 011 100 101 110 111 Output 1 SYEN 3330 Digital Systems

DFF Implementation Moving State Table Data to a K-Map and Solving: LDS Q LDS Data_in CLS 1 SYEN 3330 Digital Systems

JKFF Implementation Moving State Table Data to a K-Map and solving: LDS LDS KQ X X X X JQ 1 X X X X CLS CLS 1 1 1 1 X X Q X X Q 1 X X X X Data_in Data_in SYEN 3330 Digital Systems

Review: Excitation Tables SYEN 3330 Digital Systems