Chapter 9 Instruction Sets: Characteristics and Functions

Contents Machine Instruction Characteristics Types of Operands Pentium II and PowerPC Data Types Types of Operations Pentium II and PowerPC Operation Types Assembly Language Stacks Little-, Big-, and Bi-Endian 2

What is an instruction set? Machine instruction characteristics The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by assembly codes 2

Instruction Cycle State Diagram Machine instruction characteristics 3

Elements of a Machine Instruction characteristics Operation code (Op code) Do this Source Operand reference To this Result Operand reference Put the answer here Next Instruction Reference When you have done that, do this... 3

Where have all the Operands gone? Machine instruction characteristics Long time passing…. (If you don’t understand, you’re too young!) Three areas including source and result operands Main memory (or virtual memory or cache) CPU register I/O device 4

Instruction Representation Machine instruction characteristics A Simple Instruction Format In machine code each instruction has a unique bit pattern During instruction execution, and instruction is read into an IR in the CPU which must be able to extract the data from the various instruction fields to perform the required operation 5

Instruction Representation Machine instruction characteristics For human consumption (well, programmers anyway) a symbolic representation is used e.g. ADD, SUB, LOAD Common examples ADD Add SUB Subtract MPY Multiply DIV Divide LOAD Load data from memory STOR Store data to memory Operands can also be represented in this way ADD A,B 5

Instruction Types Example X = X + Y Machine instruction characteristics Example X = X + Y Assume that the variable X and Y correspond to locations 513 and 514 Operation Load a register with the contents of memory location 513 Add the contents of memory location 514 to the register Store the contents of the register in memory location 513 6

Instruction Types Data processing Data storage (main memory) Machine instruction characteristics Data processing Data storage (main memory) Data movement (I/O) Program flow control 6

Number of Addresses 3 addresses Operand 1, Operand 2, Result Machine instruction characteristics 3 addresses Operand 1, Operand 2, Result a = b + c; May be a forth - next instruction (usually implicit) Not common Needs very long words to hold everything Instruction Comment SUB Y,A,D Y ← A – B MPY T,D,E T ← D × E ADD T,T,C T ← T + C DIV Y,Y,T Y ← Y ÷ T 7

Number of Addresses 2 addresses Machine instruction characteristics 2 addresses One address doubles as operand and result a = a + b Reduces length of instruction Requires some extra work Temporary storage to hold some results Instruction Comment MOVE Y,A Y ← A SUB Y,B Y ← Y – B T,D T ← D MPY T,E T ← T × E ADD T,C T ← T + C DIV Y,T Y ← Y ÷ T 8

Number of Addresses 1 address Implicit second address Machine instruction characteristics 1 address Implicit second address Usually a register (accumulator) Common on early machines Instruction Comment LOAD D AC ← D MPY E AC ← AC × E ADD C AC ← AC + C STOR Y Y ← AC A AC ← A SUB B AC ← AC – B DIV AC ← AC ÷ Y 9

Number of Addresses 0 (zero) addresses All addresses implicit Machine instruction characteristics 0 (zero) addresses All addresses implicit Uses a stack e.g. push a push b add pop c c = a + b 10

Utilization of Instruction Addresses Machine instruction characteristics Number of Address Symbolic Representation Interpretation 3 OP A,B,C A ← B OP C 2 OP A,B A ← A OP B 1 OP A AC ← AC OP A OP T ← (T-1) OP T AC = accumulator T = top of stack A,B,C = memory or register locations 11

How Many Addresses More addresses Fewer addresses Machine instruction characteristics More addresses More complex (powerful?) instructions More registers Inter-register operations are quicker Fewer instructions per program Fewer addresses Less complex (powerful?) instructions instructions of shorter length More instructions per program Faster fetch/execution of instructions more total instructions longer execution times and longer,more complex programs 11

Number of Addresses One-address instruction Machine instruction characteristics One-address instruction one general-purpose register (accumulator) Multiple-address instruction multiple general-purpose register Issue of whether an address references a memory location or a register A machine may offer variety of addressing modes 11

Design Decisions Operation repertoire Data types Instruction formats Machine instruction characteristics Operation repertoire How many ops? What can they do? How complex are they? Data types Instruction formats Length of op code field Number of addresses Registers Number of CPU registers available Which operations can be performed on which registers? 12

Design Decisions Addressing modes (later…) RISC vs CISC Machine instruction characteristics Addressing modes (later…) RISC vs CISC 13

Types of Operand Addresses Numbers Characters Logical Data Types of operands Addresses Numbers Characters Logical Data 14

Numbers A limit to the magnitude of numbers representable on a machine Types of operands A limit to the magnitude of numbers representable on a machine A limit to their precision in the case of floating-point numbers rounding, overflow and underflow Three types of numerical data Integer of fixed point Floating point Decimal 14

Characters ASCII code(unique 7-bit pattern,128 characters) Types of operands ASCII code(unique 7-bit pattern,128 characters) 14

Characters Types of operands The eighth bit may be set to 0 or used as a parity bit for error detection Bit pattern 011XXXX, the digits 0 through 9 are represented by their binary equivalents, 0000 through 1001, in the right-most 4 digits Extended Binary Coded Decimal Interchange Code (EBCDIC) 14

Logical Data Two advantages to the bit-oriented view Types of operands Two advantages to the bit-oriented view Store an array of Boolean or binary data items, in which each item can take on only the values 1 and 0 Manipulate the bits of a data item 14

Pentium II Data Types 8 bit Byte 16 bit word 32 bit double word Pentium II and PowerPC data types 8 bit Byte 16 bit word 32 bit double word 64 bit quad word Addressing is by 8 bit unit A 32 bit double word is read at addresses divisible by 4 15

Specific Data Types General - arbitrary binary contents Pentium II and PowerPC data types General - arbitrary binary contents Integer - single binary value Ordinal - unsigned integer Unpacked BCD - One digit per byte Packed BCD - 2 BCD digits per byte Near Pointer - 32 bit offset within segment Bit field Byte String Floating Point 16

Pentium II Numerical Data Formats Pentium II and PowerPC data types 16

Pentium II Numerical Data Formats Pentium II and PowerPC data types 16

PowerPC Data Types Data types recognized by fixed-point processor Pentium II and PowerPC data types Data types recognized by fixed-point processor Unsigned byte used for logical or integer arithmetic operations loaded from memory into a general register by zero extending on the left to the full register size Unsigned halfword as for unsigned bytes, but, for 16-bit quantities Signed halfword used for arithmetic operations loaded into memory by sign extending on the left to full register size 17

PowerPC Data Types Unsigned word Pentium II and PowerPC data types Unsigned word used for logical operations and as an address pointer Signed word used for arithmetic operations Unsigned doubleword used as an address pointer Byte string from 0 to 128 bytes in length 17

Types of Operation Data Transfer Arithmetic Logical Conversion I/O operations Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control 18

Common Instruction Set Operation Types of operations 18

Common Instruction Set Operation Types of operations 18

Common Instruction Set Operation Types of operations 18

CPU Actions for Various Types of Operations 18

Data Transfer Types of operations Specify Source Destination Amount of data May be different instructions for different movements e.g. IBM 370 Or one instruction and different addresses e.g. VAX 19

IBM S/370 Data Transfer Operations Types of operations 19

Arithmetic Add, Subtract, Multiply, Divide Signed Integer Types of operations Add, Subtract, Multiply, Divide Signed Integer Floating point ? May include Increment (a++) Decrement (a--) Negate (-a) 20

Logical Bitwise operations AND, OR, NOT Types of operations Bitwise operations AND, OR, NOT Logical shift : the bits of a word are shifted left or right. On one end, the bit shifted out is lost Arithmetic shift : treats the data as a signed integer and does not shift the sigh bit 21

Shift and Rotate Operations Types of operations 19

Shift and Rotate Operations Types of operations 19

Conversion change the format or operate on the format of data Types of operations change the format or operate on the format of data E.g. Binary to Decimal 22

Input/Output May be specific instructions Types of operations May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA) 23

Systems Control Executed only while CPU needs to be in specific state Types of operations Executed only while the processor is in a certain privileged state the processor is executing a program in a special privileged area of memory CPU needs to be in specific state Ring 0 on 80386+ Kernel mode For operating systems use 24

Transfer of Control Branch e.g. branch to x if result is zero Types of operations Branch e.g. branch to x if result is zero conditional branch instruction two ways of generating the condition most machines provide a 1-bit or multiple-bit condition code that is set as the result of some operations to perform a comparison and specify a branch in the same instruction 25

Branch Instructions Types of operations 25

Transfer of Control Skip implied address Types of operations Skip implied address the implied address equals the address of the next instruction plus one instruction length e.g. increment and skip if zero ISZ Register1 Branch xxxx ADD A 25

Transfer of Control Procedure Call Instructions Types of operations Procedure Call Instructions self-contained computer program incorporated into a larger program Two principal reasons for the use of procedures economy and modularity Two basic instructions a call instruction branching from the present location to the procedure return instruction returning from the procedure to the place from which it was called 25

Transfer of Control Types of operations Nested Procedures 25

Transfer of Control Types of operations A procedure can be called from more than one location A procedure call can appear in a procedure allows the nesting of procedures to an arbitrary depth Each procedure call is matched by a return in the called program 25

Transfer of Control Procedure Call Instructions (continued) Types of operations Procedure Call Instructions (continued) CPU must somehow save the return address the return can take place appropriately Common places for storing the return address Register Start of procedure Top of stack 25

Transfer of Control Procedure Call Instructions (continued) Types of operations Procedure Call Instructions (continued) If the register approach is used CALL X causes the following actions RN ← PC + △ PC ← X RN : register always used for this purpose △ : instruction length If storing the return address at the start of the procedure CALL X causes X ← PC + △ PC ← X + 1 25

Transfer of Control Procedure Call Instructions (continued) Types of operations Procedure Call Instructions (continued) The only limitation of these approaches Prevention the use of reentrant procedures A reentrant procedure is one in which it is possible to have several cells open to it an the same time A more general and powerful approach Stack When CPU executes a call it places the return address on the stack 25

Transfer of Control Types of operations Use of Stack 25

Transfer of Control Procedure Call Instructions (continued) Types of operations Procedure Call Instructions (continued) necessary to pass parameters(can be passed in registers) with a procedure call possible to store the parameters in memory just after the CALL instruction more flexible approach to parameter passing stack Entire set of parameters, including return address, stored for a procedure invocation stack frame 26

Transfer of Control Types of operations 26

Pentium II Operation Types Pentium II and PowerPC operation types 26

Pentium II Operation Types Pentium II and PowerPC operation types 26

Pentium II Operation Types Pentium II and PowerPC operation types 26

Pentium II Operation Types Pentium II and PowerPC operation types 26

Call/Return Instructions Pentium II and PowerPC operation types CALL instruction pushes the current instruction pointer value onto the stack causes a jump to the entry point of the procedure by placing the address of the entry point in the instruction pointer ENTER instruction added to the instruction set to provide direct support for the compiler 26

Pentium II Condition Codes Pentium II and PowerPC operation types 26

Pentium II Conditions Pentium II and PowerPC operation types 26

Pentium II Conditions With comparison two numbers as signed integers Pentium II and PowerPC operation types With comparison two numbers as signed integers use the terms less than and greater than With comparison them as unsigned integers use the terms below and above 26

Pentium II MMX Instructions Pentium II and PowerPC operation types 57 new instructions treating data in a SIMD fashion possible to perform the same operation, such as addition or multiplication, on multiple data elements at once Each data type is 64-bits in length and consists of multiple smaller data fields, each of which holds a fixed-point integer Packet byte Packed word Packed doubleword 26

MMX Instruction Set Pentium II and PowerPC operation types 26

MMX Instruction Set Pentium II and PowerPC operation types 26

Image Compositing Alpha Alpha B B G G R R Image A Image A 1. Pentium II and PowerPC operation types Alpha Alpha B B G G R R Image A Image A Ar3 Ar2 Ar1 Ar0 Br3 Br2 Br1 Br0 1. Unpack byte R pixel components from images A and B Ar3 Ar2 Ar1 Ar0 Br3 Br2 Br1 Br0 Subtract 2. Subtract image B from image A Ar3 Ar2 Ar1 Ar0 26

Image Compositing 2. Subtract image B from image A 3. Pentium II and PowerPC operation types 2. Subtract image B from image A r3 r2 r1 r0 × 3. Multiply result by fade value fade Fade×r3 Fade×r2 Fade×r1 Fade×r0 + 4. Add image B pixels Br3 Br2 Br1 Br0 newr3 newr2 newr1 newr0 5. Pack new composit pixels Back to bytes r3 r2 r1 r0 26

Image Compositing MMX code sequence performing this operation Pentium II and PowerPC operation types MMX code sequence performing this operation pxor mm7, mm7 ; zero out mm7 movq mm3, fad_val ; load fade value replicated 4 times movd mm0, image A ; load 4 red pixel components from image A mm1, image B ; load 4 red pixel components from image B punpckblw mm0, mm7 ; unpack 4 pixels to 16bits mm1, mm7 psubw mm0, mm1 ; subtract image B from image A pmulhw mm0, mm3 ; multiply the subtract result by fade values padddw ; add result to image B packuswb ; pack 16bit results back to bytes 26

PowerPC Operation Types Pentium II and PowerPC operation types 26

PowerPC Operation Types Pentium II and PowerPC operation types 26

Load/Store Instructions Pentium II and PowerPC operation types accesses memory locations in the PowerPC architecture arithmetic and logical instructions performed only on registers Two features characterizing the different load/store instructions Data size Sign extension 26

Assembly Language N = I + J + K (initialize I,J and K to 2,3,4) Computation of the Formula N = I + J + K 26

Assembly Language The program starts in location 101(hexadecimal) Memory reserved for the four variables starting at location 201 Four consisted instructions Load the contents of location 201 into the AC Add the contents of location 202 to the AC Add the contents of location 203 to the AC Store the contents of the AC in location 204 Symbolic name or mnemonic of each instruction 26

Assembly Language Assembly language Use of the symbolic name or mnemonic of each instruction The first field contains the address of a location The second field contains the three-letter symbol for the opcode With memory-referencing instruction, a third field contains the address Pseudoinstruction 26

Assembly Language Use of symbolic addresses The first field still for the address a symbol used instead of an absolute numerical address 26

Assembly Language Assembly language Assembly programs are translated into machine language by an assembler This program not only does the symbolic translation discussed earlier, but also assigns some form of memory addresses to symbolic addresses 26

Stacks Stacks An ordered set of elements, only one of which can be accessed at a time The point of access is called the top of the stack The number of elements in the stack, or length of the stack, is variable Also known as a pushdown list or a last-in-first-out(LIFO) list 26

Stack-Oriented Operations Stacks PUSH Append a new element on the top of the stack POP Delete the top element of the stack Unary Operation Perform operation on top element of stack. Replace top element with result Binary Perform operation on top elements of stack. Delete top two elements of stack. Place result of operation on top of stack 26

Typical Stack Organizations Stacks Three addresses needed for proper operation Stack pointer Stack base Stack limit 26

Typical Stack Organizations Stacks To speed up stack operations, the top two stack elements are often stored in registers 26

Expression Evaluation Stacks Applied rules for each element of the expression If the element is a variable or constant, push it onto the stack If the element is an operator, pop the top tow items of the stack, perform the operation, and push the result 26

Comparison of Programs to Calculate f = (a-b)/(c+d×e) Stacks 26

Use of Stack to Compute f = (a-b)/(d×e+c) Stacks 26

Conversion of an Expression Stacks 26

Byte Ordering big-endian little-endian Little-, big-, and bi-endian big-endian The mapping on the left stores the most significant byte in the lowest numerical byte address IBM System 370/390, the Motorola 680×0, Sun SPARC, and most RISC machines little-endian The mapping on the right stores the least significant byte in the lowest numerical byte address Intel 80x86, Pentium II, VAX, and Alpha presents problems when data are transferred from a machine of one endian type to the other 26

C Data Structure and its Endian Maps Little-, big-, and bi-endian 26

Another View Little-, big-, and bi-endian 26

Byte Ordering Little-, big-, and bi-endian No general consensus as to which is the superior style of endianness. Points favoring the big-endian style Character-string sorting Decimal / ASCII dumps Consistent order points favoring the little-endian style big-endian processor has to perform addition when it converts a 32-bit integer address to a 16-bit integer address, to use the least significant bytes easier to perform higher-precision arithmetic not required to find least-significant byte and move backward 26

Byte Ordering Little-, big-, and bi-endian PowerPC is a bi-endian processor that supports both big-endian and little-endian modes The bi-endian architecture enables software developers to choose either mode when migrating operating systems and applications from other machines To support this hardware feature, 2 bits are maintained in the machine in the MSR maintained by the operating system as part of the process state 26

Bit Ordering Questions faced with in ordering the bits within a byte Little-, big-, and bi-endian Questions faced with in ordering the bits within a byte Do you count the first bit as bit zero or as bit one? Do you assign the lowest bit number to the byte’s least significant bit(little endian) or to the bytes most significant bit(big-endian) 26