EEE2243 Digital System Design Chapter 9: Advanced Topic: Physical Implementation by Muhazam Mustapha extracted from Frank Vahid’s slides, May 2012

Learning Outcome By the end of this chapter, students are expected to understand some methodologies in IC production and aware about the current fabrication techologies

Chapter Content Application Specific IC (ASIC) Field Programmable Gate Array (FPGA) Other Technologies: 74 Series SPLD PLD

ASIC

Manufactured IC Technologies We can manufacture our own IC Months of time and millions of dollars (1) Full-custom or (2) semicustom (1) Full-custom IC We make a full custom layout Using CAD tools Layout describes the location and size of every transistor and wire A fab (fabrication plant) builds IC for layout Hard! Fab setup costs ("non-recurring engineering", or NRE, costs) high Error prone (several "respins") Fairly uncommon Reserved for special ICs that demand the very best performance or the very smallest size/power B elt W a r n k p w C us t om l a y out s IC F ab mo n ths

Gate Array ASIC (2) Semicustom IC (2a) Gate array "Application-specific IC" (ASIC) (a) Gate array or (b) standard cell (2a) Gate array Series of gates already layed out on chip We just wire them together Using CAD tools Vs. full-custom Cheaper and quicker to design But worse performance, size, power Very popular k B elt W a r n p w s ( b ) ( a ) k p s ( c ) IC ( d ) w w eeks ( just wi r ing) F ab

Half-adder equations: Gate Array ASIC (2a) Gate array Example: Mapping a half-adder to a gate array Half-adder equations: s = a'b + ab' co = ab a c o ab a'b ab' b s G a t e a r r a y

FPGA

Programmable IC Technology – FPGA Manufactured IC technologies require weeks to months to fabricate And have large (hundred thousand to million dollar) initial costs Programmable ICs are pre-manufactured Can implement circuit today Just download bits into device Slower/bigger/more-power than manufactured ICs But get it today, and no fabrication costs Popular programmable IC – FPGA "Field-programmable gate array" Developed late 1980s Though no "gate array" inside Named when gate arrays were very popular in the 1980s Programmable in seconds

FPGA Internals: Lookup Tables (LUTs) Basic idea: Memory can implement combinational logic e.g., 2-address memory can implement 2-input logic 1-bit wide memory – 1 function; 2-bits wide – 2 functions Such memory in FPGA known as Lookup Table (LUT) F = x'y' + xy ( d ) F = x'y' + xy G = xy' x 1 y F G 4x 1 Mem. 4x 1 Mem. 1 2 3 rd a1 a0 D ( c ) 4x 2 Mem. 10 00 01 1 2 3 rd a1 a0 x y D1 D0 F G ( e ) x y F 1 rd 1 1 y=0 x=0 F=1 1 1 1 2 1 1 1 3 x a1 y a0 D F ( a ) ( b )

FPGA Internals: Switch Matrices Previous slides had hardwired connections between LUTs Instead, want to program the connections too Use switch matrices (also known as programmable interconnect) Simple mux-based version – each output can be set to any of the four inputs just by programming its 2-bit configuration memory ( b ) m0 o0 o1 i0 s0 d s1 i1 i2 i3 m1 m2 m3 2-bit memory Switch matrix 4x 1 mux FPGA (partial) 8x 2 Mem. 8x 2 Mem. 00 00 1 00 1 00 2 00 2 00 P0 3 00 3 00 P6 P1 a2 a2 4 00 4 00 P2 a1 m0 m1 o0 o1 m2 m3 Switch matrix a1 P7 a0 5 00 a0 5 00 P3 6 00 6 00 7 00 7 00 D1 D0 D1 D0 P8 P9 P4 P5 ( a )

FPGA Internals: Configurable Logic Blocks (CLBs) LUTs can only implement combinational logic Need flip-flops to implement sequential logic Add flip-flop to each LUT output Configurable Logic Block (CLB) LUT + flip-flops Can program CLB outputs to come from flip-flops or from LUTs directly FPGA CLB CLB 8x 2 Mem. 8x 2 Mem. 00 00 1 00 1 00 2 00 2 00 P0 3 00 3 00 P1 a2 a2 a1 4 00 a1 4 00 P2 00 o0 P3 a0 5 00 a0 5 00 m0 o1 m1 00 6 00 6 00 m2 7 00 m3 7 00 flip-flop CLB output D1 D0 Switch D1 D0 matrix 2x 1 1-bit CLB output configuration memory P6 P7 P8 P9 P4 P5

FPGA Internals: Sequential Circuit Example using CLBs d CLB CLB 8x 2 Mem. 8x 2 Mem. 11 10 01 00 00 01 10 11 1 1 2 2 3 3 a b a2 a2 w x y z 4 00 4 00 a1 10 11 o0 a1 ( a ) a0 5 a0 5 m0 o1 6 m1 6 m2 7 m3 7 Left lookup table D1 D0 Switch D1 D0 a2 a1 a0 D1 D0 matrix a b w=a' x=b' 1 1 1 1 1 1 1 1 1 2 x1 2 x1 1 2 x1 2 x1 1 1 1 1 z y x w below unused ( b ) d c ( c )

FPGA Internals: Overall Architecture Consists of hundreds or thousands of CLBs and switch matrices (SMs) arranged in regular pattern on a chip Represents channel with tens of wires Connections for just one CLB shown, but all CLBs are obviously connected to channels CLB CLB CLB SM SM CLB CLB CLB SM SM CLB CLB CLB

Other Technologies

7400 Series Off-the-shelf logic (SSI) IC Logic IC has a few gates, connected to IC's pins Known as Small Scale Integration (SSI) Popular logic IC series: 7400 Originally developed 1960s Back then, each IC cost $1000 Today, costs just tens of cents V C C I 14 I 13 I 12 I 11 I 10 I 9 I 8 I C I 1 I 2 I 3 I 4 I 5 I 6 I 7 GND

7400 Series

7400 Series Example: Seat belt warning light using off-the-shelf 7400 ICs Option 1: Use one 74LS08 IC having 2-input AND gates, and one 74LS04 IC having inverters (a) Desired circuit I 14 I 13 I 12 I 11 I 10 I 9 I 8 k (c) Connect ICs to create desired circuit p w 74LS08 I C s n I 1 I 2 I 3 I 4 I 5 I 6 I 7 w k ( a ) p (b) Decompose into 2-input AND gates k p s w n ( b ) I 14 I 13 I 12 I 11 I 10 I 9 I 8 s 74LS04 I C I 1 I 2 I 3 I 4 I 5 I 6 I 7 ( c )

Connecting the pins to create the desired circuit 7400 Series Example: Seat belt warning light using off-the-shelf 7400 ICs Option 2: Use a single 74LS27 IC having 3-input NOR gates k p w s w I 14 I 13 I 12 I 11 I 10 I 9 I 8 s k ( a ) 74LS27 I C Converting to 3-input NOR gates ( b ) s p k w p I 1 I 2 I 3 I 4 I 5 I 6 I 7 ( c ) Connecting the pins to create the desired circuit

Simple Programmable Logic Devices (SPLDs) 1 I 2 I 3 Developed 1970s (thus, pre-dates FPGAs) Prefabricated IC with large AND-OR structure Connections can be "programmed" to create custom circuit Circuit shown can implement any 3-input function of up to 3 terms e.g., F = abc + a'c' O1 PLD I C programmable nodes

SPLD – Programmable Nodes Fuse based – "blown" fuse removes connection Memory based – 1 creates connection O1 PLD I C 3 2 1 programmable nodes p r o g r ammable node Fuse based ( a ) F use "unbl o wn" fuse "bl o wn" fuse Memory based mem mem 1 ( b )

PLD with programmable registered outputs PLD Extensions I 3 2 1 ( a ) PLD C O1 O2 b FF × programmable bit clk Two-output PLD PLD with programmable registered outputs

More on PLD-s Originally (1970s) known as Programmable Logic Array – PLA Had programmable AND and OR arrays AMD created "Programmable Array Logic" – "PAL" (trademark) Only AND array was programmable (fuse based) Lattice Semiconductor Corp. created "Generic Array Logic – "GAL" (trademark) Memory based As IC capacities increased, companies put multiple PLD structures on one chip, interconnecting them Become known as Complex PLDs (CPLD), and older PLDs became known as Simple PLDs (SPLD) GENERAL difference of SPLDs vs. CPLDs vs. FPGAs: SPLD: tens to hundreds of gates, and usually non-volatile (saves bits without power) CPLD: thousands of gates, and usually non-volatile FPGA: tens of thousands of gates and more, and usually volatile (but no reason why couldn't be non-volatile)