ELEC 7770 Advanced VLSI Design Spring 2012 A Linear Programming Solution to Clock Constraint Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12/course.html Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

A General Sequential Circuit Inputs Outputs Combinational Logic Registers Clock Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

A Level-Sensitive Latch D QN Q CK Clock period, Tck CK Latch open Latch closed Latch open time Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Alternative Implementation D Q CK J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Wiley Interscience, 2004, p.137. Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Data Must be Stable Before Latch Closes 0→1→0→0→ D = 0 → 1 → 1 1 1→0→1→0→1→ QN delays 1 Q 1 CK = 1 → 1 → 0 0→0→1→0→1→ 1→1→0→0→ Unstable state Clock period, Tck CK Latch open Latch closed time Stable data Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Data and Clock Parameters Clock period, Tck CK Latch open Latch closed time Stable data D time Setup time Hold time Q Stable Q time CK-to-Q delay Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Design With Level-Sensitive Latches PI PI Comb. Logic Comb. Logic Level-sens. Latches Level-sens. Latches PO PO CK Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Edge-Triggered Flip-flop Master latch Slave latch D Q QN CK Hold time Clock period, Tck CK Master open Slave open time Setup time Trigger edges CK-to-Q Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

A Dynamic Implementation VDD CK CK D Q CK CK GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 229. Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

A Static Implementation VDD Q CK CK D CK CK GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 230. Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Design With Edge-Triggered Flip-Flops Inputs Outputs Combinational Logic Flip-flops Clock Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Setup Time Constraint Skew si Skew sj Combinational path delay Arrive no later than this FF i FF j δ(i,j) ≤ d(i,j) ≤ Δ(i,j) Note: All times for a FF should be adjusted by its clock skew. Travel time Tsi Thi Tsj time Tqi Tck Clock edge Constraint: si + Tqi + Δ(i,j) ≤ sj + Tck – Tsj i.e., Δ(i,j) ≤ Tck – Tsj – Tqi + sj – si This is known as long path constraint – prevents zero clocking Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

ELEC 7770: Advanced VLSI Design (Agrawal) Hold Time Constraint Combinational path delay Skew si FF i FF j Skew sj δ(i,j) ≤ d(i,j) ≤ Δ(i,j) Note: All times for a FF should be adjusted by its clock skew. sj – si + Thj Tsi Thi Tsj time Tqi Tck Clock edge (si) Constraint: si + Tqi + δ(i,j) ≥ sj + Thj i.e., δ(i,j) ≥ Thj – Tqi + sj – si This is known as short path constraint – avoids double clocking Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Solving Hold Time Problem (1) PO (FFj) PI (FFi) PO PI PO (FFi) PI (FFj) Fanout node External edges (variable delays) Internal edges (fixed delays) Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Solving Hold Time Problem (2) Variables: Shortest arrival time at node i = ai Longest arrival time at node i = Ai Buffer delay on external edge (i,j) = wij Constants: At PI i: Ai = Λi and ai = λi, user specified. At PI (FF) i: Ai = ai = Tqi Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Solving Hold Time Problem (3) Constraints: At PO i: Ai ≤ Ri and ai ≥ ri, user defined. At PO (FF) i: ai ≥ Thi, short path constraint. Ai ≤ Tck – Tsi, long path constraint. Optimization function (a linear approximation to minimum number of delay buffers): minimize ∑ wij all external edges (i,j) Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Linear Programming Solution (1) minimize ∑ wij all external edges (i,j) Subject to: Aj ≥ Ai + wij for all i ε Fanin(j) aj ≤ ai + wij for all i ε Fanin(j) Ai ≤ Ri for all i ε PO ai ≥ ri for all i ε PO Ai ≤ Tck – Tsi for all i ε PO(FF i) ai ≥ Thi for all i ε PO(FF i) Ai = Λi for all i ε PI ai = λi for all i ε PI Ai = Tqi for all i ε PI(FF i) ai = Tqi for all i ε PI(FF i) Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Linear Programming Solution (2) Solution inserts smallest delays in interconnects to satisfy short path constraints. Maintains the specified clock period and satisfies setup time constraints. Reference: N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Shift Register Example 1 (Long Path) Δ Δ CK s1 s2 s3 Delay ≤ Δ Delay ≤ Δ Zero skew su ho su ho su ho t Ck-2-Q Ck-2-Q Ck-2-Q T 2T Δ ≤ Delay Δ ≤ Delay su ho su ho su ho t Ck-2-Q Ck-2-Q Ck-2-Q s1 T s2 2T s3 Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Shift Register Example 1 (Short Path) δ δ CK s1 s2 s3 Zero skew F1 su ho su ho su ho t Ck-2-Q Ck-2-Q Ck-2-Q T 2T δ≥ Delay su ho su ho su ho t Ck-2-Q Ck-2-Q Ck-2-Q Zero skew F2 T 2T Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Shift Register Example 1 (Short Path) δ δ CK s1 s2 s3 F1 su ho su ho su ho t Ck-2-Q Ck-2-Q Ck-2-Q s1 2T T δ≥ Delay F2 su ho T su ho 2T su ho t Ck-2-Q Ck-2-Q Ck-2-Q s2 Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal) nonzero skew F2

Shift Register Example 2 (Short Path) δ δ CK s1 s2 s3 F1 su ho T su ho 2T su ho t Ck-2-Q Ck-2-Q Ck-2-Q s2 δ ≥ Delay su ho Ck-2-Q t T 2T F2 s1 Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)

Shift Register Example 2 (Long Path) Δ Δ CK s1 s2 s3 Delay ≤ Δ Delay ≤ Δ Zero skew su ho su ho su ho t Ck-2-Q Ck-2-Q Ck-2-Q T 2T Δ ≤ Delay Δ ≤ Delay su ho su ho su ho t Ck-2-Q Ck-2-Q Ck-2-Q s1 s3 T s2 2T Spring 2012, Feb 27 . . . ELEC 7770: Advanced VLSI Design (Agrawal)