Progress Report 2014/04/23

Big-LITTLE Core Scheduling Two approaches Loading-based Classify-first

Big-LITTLE Core Scheduling Two approaches Loading-based Classify-first

Loading-based Approach Strategy from Linaro. Track task loading during runtime. Assign tasks with heavy loading to big core. However, may not be energy-efficient while scheduling certain kinds of tasks.

Resource-guided Approach Instead of using loading of a task, we define “resource” for each task. “Minimum resource required” By providing the least possible CPU cycles, we can reduce power consumption while meeting QoS requirement. “Minimum resource required” is the amount of CPU cycles a task should be allocated in order to satisfy its QoS requirement.

Resource-guided Approach(Cont.) However, it is hard to define “resource” for every task in the system. QoS requirement is subjective. Some tasks do not have QoS requirement.

A Mixed Approach Between loading-based and resource- guided. “Only define resource for those tasks with heavy loading”

Big-LITTLE Core Scheduling Two approaches Loading-based Classify-first

Classify-first Approach Decide the bias of a task before scheduling. Big-core bias or little-core bias During scheduling, assign the task to some specific cores according to its bias. Change task’s affinity/CPU mask

Classify-first Approach(Cont.) How to decide the bias of a task? Profiling What about runtime? Some researches use hardware counters to predict task performance for different core types. Performance Impact Estimation(PIE)

Power-Performance Modeling on Asymmetric Multi-Cores Predict CPI and power consumption of core P’ from information of core P. missPX and latencyPX are the number of occurrences and latency of each occurrence of the miss event X on processor P. NX is fraction of instructions of type X in instruction mix.

Power-Performance Modeling on Asymmetric Multi-Cores(Cont.) missPX and latencyPX are the number of occurrences and latency of each occurrence of the miss event X on processor P. NX is fraction of instructions of type X in instruction mix.

MediaTek CorePilot “Delivering extreme compute performance with maximum power efficiency”

MediaTek CorePilot Scheduler Delivers a true heterogeneous compute model by using a scheduling algorithm that assigns tasks to two different schedulers, according to their priority – the Heterogeneous Multi-Processing (HMP) scheduler and Real-Time (RT) scheduler.

The MediaTek HMP Scheduler

Better Performance

Power-efficiency