Design for Simple Spiking Neuron Model Mixed-Signal Circuit Design for Simple Spiking Neuron Model Abdullah H. Ozcan Vamshi Chatla ECE 6332 – Fall 2009 University of Virginia

Motivation - 10^11 neurons, each neuron 10-10^5 synapses - Uses less power than your refrigerator light - Power matters; decreasing energy/spike

Outline - ADC Circuit - Neuron Circuit - Conclusion

TIQ Based ANALOG TO DIGITAL CONVERTER

Comparator Stage

Gain Booster Stage Sharper Transitions in the output Full voltage swing 7

XOR Stage - Converts TC Code to 1 out of N code

Encoder Stage (Fat Tree)

Simulation Results

Lowering Supply Voltage

ADC results without gain booster stage

ADC results using gain booster stage

- Technology: 0.6 um - Avg Power: 14.2 mW (14.0 mW) ADC (4bit) Summary - Technology: 0.6 um - Avg Power: 14.2 mW (14.0 mW) - Max Power: 23.9 mW - Transistors used: 360 - Supply Voltage: 5 V Analog Range: 1 V Sampling Rate: 200 MHz 6bit ADC 6 bit ADC (TIQ) (Fat Tree Encoder) (ROM Encoder) Technology 0.6 um 0.18 um 0.25 um Max Speed 0.2 GSPS 2.00 GSPS 1.11 GSPS Power Consumption Avg 380 mW Avg. 22 mW Max 38.65 mW Avg 32.64 mW Max 54.41 mW Transistor Count - 485 2803

Izhikevich’s Simple Spiking Neuron Model

VLSI Circuit of Izhikevich’s Model (Jayawan H. B. Wijekon, Piotr Dudek (2007). Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit, Int. Joint Conference on Neural Networks)

VLSI Circuit (0.35 μm0.6 μm)

Comparator Part

Matlab Results

Circuit Results

Neuron Circuit Summary -Transistors used: 12 -142.1 mW  119.29 mW (% 17 )

QUESTIONS Thank You!