Prof. Shiyan Hu Shiyan@mtu.edu Gate Sizing Prof. Shiyan Hu Shiyan@mtu.edu

Problem Definition Given a timing (delay) target, use smallest power/area gates to meet the timing target In general, smaller power -> larger timing, smaller timing -> larger power.

Delay due to Gate Sizing Suppose that unit width gate capacitance is c and unit width gate resistance is r. Given gate size wi, Gate size wi: R  r/wi, C  cwi Delay is a function of RC Delay   RiCj   wi/wj

Wire and Gate Models

Combinatorial Circuit Model Gate size variables x1, x2, x3 Delay on each gate depends on x a1 x1 a3 a6 D1 D4 D6 D7 a5 a7 a2 a4 Drivers D2 Loads D9 D10 D3 D5 D8 x3 x2

Path Delay Express path delay in terms of component delay A component can be a gate or a wire Delay D for each component Arrival time a for some components

Gate Sizing Power/area minimization under delay constraints: This can be solved efficiently using gpsolve

Gate Sizing using GPSOLVE Follow the steps in gatesizing.m for the example in the slides of timing analysis and optimization