IBM 90nm Test Chip Results Preeti 06/014/2010

Clock-to-Data delay (0->1) 800 -> 570 (TMR = 40%) Delay = 5.1ns – 1.9ns (pad_delay) = 3.2ns CLOCK Q2_LVT Q0_RVT Delay = 5.1ns

Clock-to-Data delay (1->0) 1000 -> 500 (TMR = 100%) Delay = 7.4ns – 1.9ns (pad_delay) = 5.5ns CLOCK Q2_LVT Q0_RVT Delay = 7.4ns

Clock-to-Data Delays – Across Rp/Rap and TMRs

Measured Resistances Write current is measured to be around 290uA

Sense Amp Structure

Current Sensing Architecture

Sense Amp Delays (0->1)

Sense Amp Delays (1->0)

Pad Delay Measurement Slides

Pad Delay Measurements - Setup 1 GHz Sampling Real Time oscilloscope used to measure pad delays 500MHz Pulse Generator Real Time Oscilloscope TESTOUT REFERENCE TESTIN

Reference-to-TESTOUT delay without Chip (1) Measuring Frequency – 3.33 MHz

Reference-to-TESTOUT delay without Chip (2) Delay between the reference and TESTOUT is 5.3ns REFERENCE TESTOUT

Reference-to-TESTOUT delay with Chip (1)

Reference-to-TESTOUT delay with Chip (2) Delay between the reference and TESTOUT is 7.2 ns Simulated Delay at TT corner = 1.84 ns Measured Pad-to-Pad Delay = 7.2 – 5.3 = 1.9 ns REFERENCE TESTOUT