EE 5340 Semiconductor Device Theory Lecture 27 - Fall 2003 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc L 27 Nov 25

n-channel enhancement MOSFET in ohmic region 0< VT< VG Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ e-e- e- e- e- n+ Depl Reg p-substrate Acceptors VB < 0 L 27 Nov 25

Fully biased n- channel VT calc L 27 Nov 25

Fully biased p- channel VT calc L 27 Nov 25

I-V relation for n-MOS (ohmic reg) ID non-physical ID,sat saturated VDS,sat VDS L 27 Nov 25

Universal drain characteristic ID VGS=VT+3V 9ID1 ohmic saturated, VDS>VGS-VT VGS=VT+2V 4ID1 VGS=VT+1V ID1 VDS L 27 Nov 25

Substrate bias effect on VT (body-effect) L 27 Nov 25

Body effect data Fig 9.9** L 27 Nov 25

Low field ohmic characteristics L 27 Nov 25

MOSFET circuit parameters L 27 Nov 25

MOSFET circuit parameters (cont) L 27 Nov 25

MOSFET equivalent circuit elements Fig 10.51* L 27 Nov 25

MOS small-signal equivalent circuit Fig 10.52* L 27 Nov 25

MOS channel- length modulation Fig 11.5* L 27 Nov 25

Analysis of channel length modulation L 27 Nov 25

Channel length mod- ulated drain char Fig 11.6* L 27 Nov 25

Associating the output conductance ID ID,sat VDS,sat VDS L 27 Nov 25

Implanted n-channel enhance-ment MOSFET (ohmic region) 0< VT< VG e- channel ele + implant ion Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ e-e- e- e- e- + + + + + + + + + + + + n+ Depl Reg p-substrate Acceptors VB < 0 L 27 Nov 25

Ion implantation* Range DRP Si & SiO2 Al Si3N4 Si Al & SiO2 L 27 Nov 25

“Dotted box” approx** L 27 Nov 25

Calculating xi and DVT L 27 Nov 25

References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 L 27 Nov 25