Automatic Test Pattern Generation Sungho Kang Yonsei University

Test Pattern Generation Introduction Test generation Manual generation Pseudo random generation Algorithmic (or deterministic) test generation Automatic Test Pattern Generation (ATPG) Calculate the set of test patterns from a description of the logic network and a set of assumptions called fault models

ATPG Result of ATPG Cost of ATPG Quality of the generated tests Introduction Result of ATPG Find a test pattern Redundant fault Run out of time/memory (Aborted fault) Cost of ATPG Low CPU time Quality of the generated tests High fault coverage Cost of Applying Test Small number of tests Fault Coverage # of detected faults / # of faults # of detected faults / (# of faults - # of redundant faults) (# of detected faults + # of redundant faults) / # of faults

Definition Single Fault Assumption Fault Excitation Fault Propagation Introduction Single Fault Assumption The assumption that one and only one fault is present in a given circuit at a time Fault Excitation The process of finding a sufficient set of PI values to cause the fault site in the good circuit to have a value opposite to the faulty value Fault Propagation The process of moving the effect of a fault closer to a PO Line Justification The process of finding a set of PI values which cause the line to achieve the desired value Essentially the same as backdrive with conflict resolution

Definition Implication Backtracking Reconvergent fanout Introduction Implication The process of determining the unique values implied by already assigned values The process can cause both forward and backward assignment of values Backtracking Retracing in the search space to resolve the conflict by trying alternate assignments at previously assigned nodes Should store previously determined values Reconvergent fanout A fanout node, two or more of whose branches eventually are used as inputs to the same element The element at which the branch reconverge is called the point of reconvergence

ATPG Example Introduction F output s-a-0

ATPG Example Introduction H s-a-1

2 Phase ATPG Random + Deterministic while an exit condition happens Introduction Random + Deterministic while an exit condition happens get a vector fault simulate the vector if the vector detects faults add the vector to the test set discard the faults for all remaining faults select a fault generate a vector if successful add the vector in the test set

Boolean Difference Boolean Difference

Boolean Difference Boolean Difference

Boolean Difference Boolean Difference

D Algorithm D Algorithm Introduce D and D’

D Algorithm Algorithm D frontier D drive 1) Initialize all nodes to X 2) Select a fault  3) Select a pdcf of  4) Implication (forward and backward) 5) D drive 6) If not reached PO, go to 4) 7) Line justification D frontier Set of elements whose output values are unspecified but whose input has some signal D or D’ D drive Attempts to propagate D or D’ to the output of elements

Example Primitive Cubes, Primitive D Cubes, Propagation D Cubes where D Algorithm Primitive Cubes, Primitive D Cubes, Propagation D Cubes where

D Algorithm Example D Algorithm G1 s-a-0

D Algorithm : Example D Algorithm G1 s-a-0

9V Algorithm Problem of D Algorithm Selection of fanout branch - increasing exponentially Advantage is mainly due to the higher degree of freedom At fanout point having a fanout of N, at most N attempts have to be made out D requires 2N-1

PODEM Path Oriented DEcision Making Search space on PIs Implicit space enumeration Algorithm PODEM() if (Error at PO) return SUCCESS if (test not possible) return FAILURE get an objective backtrace the objective to PI imply the PI value if PODEM() == SUCCESS imply PI with X value assume target fault is I s-a-v objective() if ( the value of I is X ) return (I, v’) select a gate(G) from the D frontier select an input j of G with value X c = controlling value of G return ( j, c’)

PODEM Example PODEM a s-a-0 : using PODEM

FAN FANout Oriented ATPG Stop the backtrace at a headline and postpone the line justification for the headline to the last Multiple backtrace Free line Gate output whose predecessors are fanout free Head line Free line that enters a region of reconvergent fanout

FAN Assume that we want to set J=0 Assume that with PI assignments previously made, setting J=0 causes D frontier empty Failure

FAN Example FAN M-L s-a-1 using FAN

X Path Check X path check Heuristics X path check Let s be a signal on the fault sensitization path If s has 0 or 1, the fault cannot be propagated Check the value using forward implication

Dominator Heuristics A signal y is said to dominate a signal x if all directed paths from x to the POs pass through y Dominator The set of signal that dominate signal x The fault effect should pass through dominators Off-path inputs of dominators are assigned noncontrolling values to propagate fault effect Example Dominators of signal C : G2 and G5 Thus D=0 and J=1

Static learning Heuristics To assign a logic value to a certain signal of the circuit, perform This is done for all signals of the circuit for both logic value 0 and 1 Example B=1 => F=1 F=0 => B=0

Dynamic Learning Heuristics If both assignments a=0 and a=1 do not result in a conflict during the implication procedure, the learning is used Example When b=1 and c=1, a=1  h=1 h=0  a=0

Recursive Learning Example Assume that I1 and J are unjustified Heuristics Example Assume that I1 and J are unjustified Verify that K=1 is necessary assignment

Test Compaction PI test values are usually partially specified Combine tests to reduce test length Two tests are compatible if they do not specify opposite values for any PI Two compatible tests Ti and Tj can be combined into one test Tij = Ti  Tj Example T1=01X, T2=0X1, T3=0X0, T4=X01 T12=011, T3=0X0, T4=X01 T13=010, T24=001

Scan Design

Sequential Test Generation Sequential ATPG Generates a sequence of vectors to detect a single stuck-at fault in sequential circuit Controllability and Observability in a sequential circuit are mush worse than those in a combinational circuit Due to the presence of memory elements Search space is too large in general No single strategy/heuristic outperforms others for all applications/circuits Can be combined with low-overhead DFT techniques such as partial scan

Topological Analysis Based Toplogical Analysis Iterative Array Model Combinational model for sequential circuit Regenerates the feedback signals from previous-time copies of the circuit A rectangle : A copy of the combinational portion of circuits

Extended D Algorithm : Example Topological Analysis Time-frame 0 : Fault activation Time-frame 1 : Fault propagation Time-frame -1 : Fault justification Time-frame -1 Time-frame 0 Time-frame 1

Extended Backtrace Algorithm(EBT) Topological Analysis Reverse Time Processing(RTP) Works backwards in time from last time-frame to first time-frame For a given fault, RTP pre-selects a path from the fault site to a primary output through several time-frames Selected path is then sensitized backwards If sensitization process fails, another path is selected Advantages of Reverse Time Processing At any time-frame, only two time-frames need to be maintain It is easier to identify repetition of state requirement Major Problems Only single-path is selected for sensitization Faults that require multiple-path sensitization for detection may not be covered The number of possible paths from the fault site to the primary outputs is very large Trying path by path is not practical

Back Algorithm Improvement of the EBT algorithm Topological Analysis Improvement of the EBT algorithm Instead of pre-selecting path, BACK algorithm pre-selects a primary output Assigns a D or D’ to the selected primary output and justifies the value backwards Testability measure(called drivability) is used to guide the backward D-justification from selected primary output to fault site Require smaller memory space Efficient than EBT number of POs < number of paths