Step 2 in behavioral modeling. Use of procedures.

Slides:



Advertisements
Similar presentations
1/8/ VerilogCopyright Joanne DeGroat, ECE, OSU1 Verilog Overview An overview of the Verilog HDL.
Advertisements

L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.
1 EE24C Digital Electronics Project Theory: Sequential Logic (part 2)
Lab 10 : Arithmetic Systems : Adder System Layout: Slide #2 Slide #3 Slide #4 Slide #5 Arithmetic Overflow: 2’s Complement Conversions: 8 Bit Adder/Subtractor.
Discussed in class and on Fridays n FSMs (only synchronous, with asynchronous reset) –Moore –Mealy –Rabin-Scott n Generalized register: –With D FFs, –With.
VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/ R.H.Khade.
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Binary additon & subtraction.
L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.
each of these is an instantiation of “full_adder”
Digital Arithmetic and Arithmetic Circuits
1/8/ L3 Data Path DesignCopyright Joanne DeGroat, ECE, OSU1 ALUs and Data Paths Subtitle: How to design the data path of a processor.
1/8/ L11 Project Step 5Copyright Joanne DeGroat, ECE, OSU1 Project Step 5 Step 2 in behavioral modeling. Use of procedures.
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.
1/8/ L7 Project Step 3Copyright Joanne DeGroat, ECE, OSU1 Project Step 4 Step 1 in transitioning to behavioral modeling. We will wire behavioral.
L26 – Datapath ALU implementation
1/8/ L7 Project Step 3Copyright Joanne DeGroat, ECE, OSU1 Project Step 3 Structural Modeling and the Generate Statement.
L12 – VHDL Overview. VHDL Overview  HDL history and background  HDL CAD systems  HDL view of design  Low level HDL examples  Ref: text Unit 10, 17,
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.
Discussed in class and on Fridays n FSMs (only synchronous, with asynchronous reset) –Moore –Mealy –Rabin-Scott n Generalized register: –With D FFs, –With.
L13 – VHDL Language Elements. VHDL Language Elements  Elements needed for FPGA design Types  Basic Types  Resolved Types – special attributes of resolved.
1/8/ L2 VHDL Introcution© Copyright Joanne DeGroat, ECE, OSU1 Introduction to VHDL.
Verilog hdl – II.
1/8/ L11 Project Step 5Copyright Joanne DeGroat, ECE, OSU1 Project Step 6 Step 3 in behavioral modeling. Use of packages.
MicroBaby ALU.
1 Introduction to Engineering Spring 2007 Lecture 19: Digital Tools 3.
1 Computer Architecture & Assembly Language Spring 2009 Dr. Richard Spillman Lecture 11 – ALU Design.
Combinational logic circuit
L5 – Sequential Circuit Design
Subtitle: How to design the data path of a processor.
Behavioral Style Combinational Design with VHDL
IAY 0600 Digital Systems Design
Modification that can be done to the datapath.
Behavioral Style Combinational Design with VHDL
Chapter 2. Introduction To VHDL
Behavioral modeling of a dual ported register set.
Chapter 4 Combinational Logic
HDL Programming Fundamentals
Project Step 2 – A single bit slice of the ALU
Modification that can be done to the datapath.
The start of a grand tour of the language.
ECE 434 Advanced Digital System L10
Incrementing and Decrementing
MicroBaby Datapath.
Copyright Joanne DeGroat, ECE, OSU
L25 – Datapath ALU.
MicroBaby Datapath.
Copyright Joanne DeGroat, ECE, OSU
Lecture 2: Continuation of SystemVerilog
ECE 434 Advanced Digital System L11
Timing & Concurrency II
ECE 352 Digital System Fundamentals
IEEE Floating Point Adder Verification
An overview of the Verilog HDL.
Behavioral modeling of a dual ported register set.
Copyright Joanne DeGroat, ECE, OSU
Structural Modeling and the Generate Statement
Project Step 2 – A single bit slice of the ALU
Copyright Joanne DeGroat, ECE, OSU
Timing & Concurrency II
Step 2 in behavioral modeling. Use of procedures.
Step 3 in behavioral modeling. Use of packages.
© Copyright Joanne DeGroat, ECE, OSU
Timing & Concurrency II
2's Complement Arithmetic
L25 – Final Review AU 15 Final Exam – Classroom – Journalism 300
Copyright Joanne DeGroat, ECE, OSU
System Controller Approach
Copyright Joanne DeGroat, ECE, OSU
Project Step 2 – A single bit slice of the ALU
Structural Modeling and the Generate Statement
Presentation transcript:

Step 2 in behavioral modeling. Use of procedures. Project Step 5 Step 2 in behavioral modeling. Use of procedures. 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

The nature of the process Will still use P, K, and R to control the operation. Previously have use P to compute Pi, K to compute Ki, and then R to generate the final result. Now will use a combined P&K&R to choose the operation being performed For op A have P,K,R of 1100,1111,1100 For op A AND B hove 1000,1111,1100 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU continued For A + B have 0110,0001,0110 Then we can use a case statement on a variable that concatenates P&K&R to choose which operation to perform. opersw := P & K & R; --Note use of variable CASE opersw IS WHEN “110011111100” => Zout <= A; Cout <= ‘0’; --op A WHEN “001111000110” => neg(A,Ztemp,CoutTemp); Zout <= Ztemp; Cout<= CoutTemp; 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU Note on operations For logical operation can do vector operations Zout <= A AND B; Where A and B are the input bit vectors Both vectors must be of the same size Arithmetic operations will need procedures One for Add One for 2’s complement One for Subtract that can be an implementation of binary subtraction, or subtraction using 2’s complement addition 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU The procedures The procedures are to be declared in the declarative region of the process In the declarative region of the process can only declare a procedure body. And thus no procedure declaration part is done. Scope of procedure is limited to just this process. (We will later move these to a package.) 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU Addition BINADD A procedure for binary addition using sequential statements. Will make the arguments to the procedure unconstrained so that it will be capable of adding words of any length (constraint that both inputs are the same index range). 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

Unconstrained declaration PROCEDURE binadd (l,r : IN BIT_VECTOR; cin : IN BIT; sum : OUT BIT_VECTOR; cout : OUT BIT) IS VARIABLE carry : BIT: --internal variable carry BEGIN carry := cin; FOR i IN l’reverse_range LOOP -- compute sum for position I -- compute carry out for position I into carry variable END LOOP; -- assign cout from final value of carry 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU Highlights on the code Inputs are “unconstrained” – they can be any size We will later use these same procedures in a package and the data size will be 16 bits. Outputs are variables Need to use attribute for loop parameter If L declared (x downto 0) such that leftmost bit is the msb and highest index THEN L’REVERSE_RANGE has the designation 0 to x 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU

Copyright 2006 - Joanne DeGroat, ECE, OSU Overall look of code Same ENTITY as before ARCHITECTURE v_3 OF adder_8 IS BEGIN --A single process as just described PROCESS (sensitivity list) PROCEDURES Local Variables opersw:= CASE opersw……. END; 1/8/2007 - L11 Project Step 5 Copyright 2006 - Joanne DeGroat, ECE, OSU