<month year> doc.: IEEE 802.15-03/125r0 August 2004 Project: IEEE P802.11 Working Group for Wireless Local Area Networks (WLANs) Submission Title: [STMicroelectronics LDPCC Proposal for 802.11n CFP] Date Submitted: [13 August 2004] Source: [Nicola Moschini, Massimiliano Siti, Stefano Valle - Andres Vila Casado, Prof. Richard Wesel] Company [STMicroelectronics, N.V.] [University of California at Los Angeles] Address [Via C. Olivetti, 2, 20041 Agrate Brianza, Italy] [405 Hilgard Avenue, 90095 Los Angeles CA] Voice: [+1 619 278 8648], FAX: [+1 858 452 3756 ] E-Mail: [{Nicola.Moschini, Massimiliano.Siti, Stefano.Valle}@ST.com] Re: [This submission presents the proposal for optional advanced coding of STMicroelectronics to the 802.11n Call For Proposals (Doc #11-03/0858r5) that was issued on 17 May 2004] Abstract: [This presentation details STMicroelectronics’ LDPCC partial proposal for IEEE 802.11 TGn. Enhancements to the 802.11-1999. Rate-compatible LDPCCs are presented as optional advanced coding technique, in order to achieve a higher coverage and/or throughput in MIMO-OFDM systems. ] Purpose: [STMicroelectronics offer this contribution to the IEEE 802.11n task group for its consideration as the solution for standardization.] Notice: This document has been prepared to assist the IEEE P802.11. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.11. N. Moschini, M. Siti, S. Valle STMicroelectronics <author>, <company>

August 2004 Outline Motivation for introducing an optional advanced coding technique in 802.11n Motivation for preferring LDPCC Variable-rate LDPCC: The principle Complexity Performance N. Moschini, M. Siti, S. Valle STMicroelectronics

Reasons for advanced coding techniques in 11n August 2004 Reasons for advanced coding techniques in 11n LDPCCs can significantly boost performances in MIMO-OFDM systems  increase the coverage and/or the throughput of the system. LDPCC is decoded iteratively  as technology improves ( more iterations) the coding gain can potentially improve The key factor for 802.11n advanced coding technique is to have multi-rate capability (i.e. good performances at every rate) and a shared HW architecture for all the rates (i.e. low cost devices) N. Moschini, M. Siti, S. Valle STMicroelectronics

Foreseen targets for advanced coding in 11n August 2004 Foreseen targets for advanced coding in 11n Code rate flexibility 1/2, 2/3 , 3/4, 5/6 Codeword flexibility range 500-2500 bit SNR gain compared to CC k=7 > 2dB Max Throughput ~540Mbps Latency < 6us Complexity < 800kgates N. Moschini, M. Siti, S. Valle STMicroelectronics

Rate-compatible structured LDPCC <month year> doc.: IEEE 802.15-03/125r0 August 2004 Rate-compatible structured LDPCC Performances of different matrices show in general slight differences for short block length (≤2000 coded bits) Implementation complexity is a key factor Structured parity check matrices allow a higher degree of decoder parallelization compared to random matrix design. Our approach yields: Rate-compatibility, i.e. good performances at every rate avoiding puncturing or shortening is essential. A common shared HW architecture for all the rates and all the codeword lengths (ensuring low cost devices) N. Moschini, M. Siti, S. Valle STMicroelectronics <author>, <company>

Variable-rate LDPC: row-combining (the idea) <month year> doc.: IEEE 802.15-03/125r0 August 2004 Variable-rate LDPC: row-combining (the idea) Rate ½ Rate ¾ Combining rows of the parity-check matrix (H) for the lowest rate code produces H for higher rates. This is equivalent to replacing a group of check nodes with a single check node that sums all the edges coming into each of the original check nodes Design criteria in Appendix B Example: rate-3/4 code from a rate-1/2 code N. Moschini, M. Siti, S. Valle STMicroelectronics <author>, <company>

Advantages of Variable-rate LDPC August 2004 Advantages of Variable-rate LDPC A new method to design LDPCC for a variety of different code rates that all share the same fundamental decoder architecture An important advantage of this approach is that all code rates have the same block length (a key performance factor) and the same variable degree distribution (an important code property). Other approaches (i.e. puncturing and shortening) suffer from performance degradation N. Moschini, M. Siti, S. Valle STMicroelectronics

Structure of the “mother” parity check matrix (rate ½) (1/2) August 2004 Structure of the “mother” parity check matrix (rate ½) (1/2) To allow efficient implementation, building blocks (red squares) have a shifted diagonal sub-matrix structure. Linear-complexity encoder based on back substitution thanks to the block-lower triangular structure. N. Moschini, M. Siti, S. Valle STMicroelectronics

Structure of the “mother” parity check matrix (rate ½) (2/2) August 2004 Structure of the “mother” parity check matrix (rate ½) (2/2) H is divided into p x p (p=27) sub-matrices that are either the all-zero matrix or a cyclic permutation of the identity matrix as: S0= S3= S7= The green block represents a bi-diagonal sub-matrix in order to avoid having p degree one variable nodes N. Moschini, M. Siti, S. Valle STMicroelectronics

Variable-rate matrices design criteria (1/2) August 2004 Variable-rate matrices design criteria (1/2) Row-combining of rows who do not have a ‘1’ in the same position  same variable node degree distribution for all rates. The selection of rows to sum preserves the lower triangular structure of through all the rates Rate 3/4: row i generated by summing row i of H of rate 1/2 code and the row with index i+M/2 where M is the total number of check equations in rate 1/2 code. N. Moschini, M. Siti, S. Valle STMicroelectronics

Variable-rate matrices design criteria (2/2) August 2004 Variable-rate matrices design criteria (2/2) Rate 2/3: generated by doing the previously described sum only for rows where i < M/3 Rate 5/6: connect three check nodes at a time, i.e.: sum of row i plus the row with index i+M/3 plus the row with index i+2M/3. On top of this the codes are designed to avoid length 4 cycles and also to have a good performance in the error floor region by conditioning the graph using the algorithms explained in [5] and [6]. N. Moschini, M. Siti, S. Valle STMicroelectronics

LDPCC parameters Codeword size 1944, 1296, 648 bits <month year> doc.: IEEE 802.15-03/125r0 August 2004 LDPCC parameters Codeword size 1944, 1296, 648 bits Code rate flexibility 1/2, 2/3, 3/4, 5/6 Codeword lengths are selected in order to minimize the padding bits of MIMO-OFDM symbols. 54 data carriers for OFDM symbol are assumed. The present proposal holds with minor changes in case of a different number of data carriers. N. Moschini, M. Siti, S. Valle STMicroelectronics <author>, <company>

Performance in AWGN channel August 2004 Performance in AWGN channel 12 iterations. Constant block size for all code-rates N. Moschini, M. Siti, S. Valle STMicroelectronics

Performance in MIMO channels August 2004 Performance in MIMO channels Simulation conditions Channel Model D - NLOS Antenna Spacing 0.5 Ch est./synch. Ideal Packet size: 1000B Detector: MMSE OFDM # of data tones 54 LDPCC Decoding Algo BCJR # iteration 12 Matrices rate-compatible N. Moschini, M. Siti, S. Valle STMicroelectronics

Performance results August 2004 N. Moschini, M. Siti, S. Valle STMicroelectronics

Performance results August 2004 N. Moschini, M. Siti, S. Valle STMicroelectronics

Performance results August 2004 N. Moschini, M. Siti, S. Valle STMicroelectronics

Performance results August 2004 N. Moschini, M. Siti, S. Valle STMicroelectronics

Variable-Rate LDPCC implementation complexity August 2004 Variable-Rate LDPCC implementation complexity The proposed LDPC code allows a very efficient HW implementation. Massive HW reuse is possible because all the rates are derived from the “mother” rate ½ and same sub-matrix size is adopted for all the codeword lengths Encoder has a linear complexity thanks to its lower triangular structure that permits the back substitution. Main targets in the table on the right can be met Area (Max) 800k gates Target Iterations 10 to 12 Decoder Freq. (Max) 240 MHz Decoding Latency 6 us N. Moschini, M. Siti, S. Valle STMicroelectronics

<month year> doc.: IEEE 802.15-03/125r0 August 2004 Conclusions The proposal contains LDPCC designed with a powerful/well performing technique to generate variable rate code up to rate 5/6. These codes result in reasonable overall complexity/latency trade-off. Performances are comparable or better than PCCC and CC Results have been obtained with 12 iterations: technology evolution will make feasible a larger number of iterations providing further gains. N. Moschini, M. Siti, S. Valle STMicroelectronics <author>, <company>