UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2017

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Presentation transcript:

UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2017 ModelSim Tutorial UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2017 Some slides are courtesy of Prof. Lin

Steps Create the project Add/create Verilog files Add testbench Compile and Simulate ECE 111 Fall 2017

Create the Project Open a new project: File > New > Project Specify a name and a location Leave the other two options as default Enter project name here Selected location ECE 111 Fall 2017

Add/Create Files Create new file: Either click on “Create New File” or right click > Add to project > New File Enter a name, Set file type to Verilog Save the file: File > Save (or ctr-S) ECE 111 Fall 2017

Add/Create Files Double click on the file or right click > edit to edit the file Add an existing file: Either click on “Create New File” or right click > Add to project > Existing file, then browse for the file Similarly, add the necessary testbench(s) ECE 111 Fall 2017

Add Testbench Testbench is a simulation specific Verilog file that is used to provide input values to the module under test. In the next two slides we provide a simple Verilog file and corresponding testbench. Detail on testbench later in the course ECE 111 Fall 2017

Add Testbench module first_module( input i1, i2, output o1, o2 ); assign o1 = i1&i2; assign o2 = i1|i2; endmodule ECE 111 Fall 2017

Add Testbench contd.. Testbench module does not have any input/output module first_module_tb; // Inputs reg i1; reg i2; // Outputs wire o1; wire o2; first_module uut ( .i1(i1), .i2(i2), .o1(o1), .o2(o2) ); Testbench module does not have any input/output The inputs will be changed inside an always/initial block Instantiate the module under test contd.. ECE 111 Fall 2017

Add Testbench initial begin i1 = 0; i2 = 0; #100; $display("%d %d %d %d\n", i1, i2, o1, o2); i2 = 1; Wait, only works in simulation Display the values, similar format as printf C , only works in simulation contd.. ECE 111 Fall 2017

Add Testbench i1 = 1; i2 = 0; #100; $display("%d %d %d %d\n", i1, i2, o1, o2); i2 = 1; end endmodule ECE 111 Fall 2017

Compile Select all the files and right click to specify compile order For simple project we can use Auto Generate to generate the order But for larger project we might need to specify the orders by ourselves Compile all after you have specified the order ECE 111 Fall 2017

Simulate Simulate > start simulation Under work > find your testbench file Click ok ECE 111 Fall 2017

Simulate Open wave tab if it did not pop up automatically In Objects tab, drag the desired input/output into the wave tab ECE 111 Fall 2017

Simulate Specify time to run and hit the run next to it ECE 111 Fall 2017