Integrating an AIG Package, Simulator, and SAT Solver Alan Mishchenko Robert Brayton Department of EECS UC Berkeley

Overview AIG, simulation, SAT Traditional use of simulation and SAT Motivation for a deeper integration Additional book-keeping Window-based computing Local fanout for nodes in to the window Local structural support for nodes the window Modified SAT solver takes advantage of the local fanout Modified simulator takes advantage of the local support Experiments Conclusion and future work 2

And-Inverter Graph (AIG) AIG is a Boolean network composed of two-input ANDs and inverters. cdab 00 01 11 10 1 F(a,b,c,d) = ab + d(ac’+bc) b c a d 6 nodes 4 levels F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d) cdab 00 01 11 10 1 a c b d 7 nodes 3 levels

Simulation Assigns particular (or random) values at the primary inputs Multiple simulation patterns are packed into 32- or 64-bit strings Simulates in a topological order Works well for AIG due to The uniformity of AND-nodes Speed of bitwise simulation Topological ordering of memory reduces CPU cache misses when accessing the simulation patterns 1 2 3 4 1 a b c d F 1 2 3 4 1 1 2 3 4 1 1 2 3 4 1 1 1 1

Boolean Satisfiability (SAT) SAT solver takes the CNF representation of the problem It performs branch-and-bound on the CNF to find a satisfying assignment, or prove that none exists a 1 2 3 4 5 6 7 8 (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + 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(¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) b b c c c d d d d d Courtesy Karem Sakallah, University of Michigan

Simulation and SAT Simulation is faster than SAT (P vs NP) This is why simulation is used before SAT to disprove easy properties However, it may take SAT a long time to disprove properties not disproved by random simulation This is why, in state-of-the-art applications, satisfying assignments returned by SAT are re-simulated to disprove more properties The problem is Re-simulting each assignment over a large AIG is very slow But, if we do not re-simulate, SAT is very slow Previous solution: batching Collect and re-simulate N (for example, N=16) assignments at once Simulation does not take too much time (but still slow) SAT solver does not slow down too much (but still slow) In this work, we propose a better solution It is based on a deeper integration of the simulator and the SAT solver

Case Study: SAT sweeping SAT sweeping computes functionally equivalent nodes, to be used in Combinational / sequential synthesis and verification Computing structural choices needed to improve area/delay after tech-mapping Transferring names from the initial netlist to the netlist after synthesis (with modifications) Optimization with don’t-cares and redundancy removal SAT sweeping is hard for AIGs with 100+ logic levels and 1M+ of nodes Efficient combination of simulation and SAT is needed In this work, SAT sweeping is used as a case-study to illustrate a deeper integration of simulation and SAT Past work on SAT sweeping F. Lu, L. Wang, K. Cheng, R. Huang. “A circuit SAT solver with signal correlation guided learning”. Proc. DATE ‘03. A. Kuehlmann, “Dynamic transition relation simplification for bounded property checking”. Proc. ICCAD ’04. A. Mishchenko, S. Chatterjee, R. Jiang, and R. K. Brayton, "FRAIGs: A unifying representation for logic synthesis and verification". ERL Technical Report, EECS Dept., UC Berkeley, March 2005.

Proposed SAT Sweeping Ecosystem

Window-Based Computation Our goals: scalability, fast runtime, low-memory Considering the whole circuit is counter-productive Instead, we consider a “moving window” Simulator and SAT solver work on nodes in the window Book-keeping info is kept only for these nodes Windowing is dynamic When computation moves to a different location, window is updated (and book-keeping information re-computed) Boolean network (AIG) Target nodes Current window Future window Previous window

Local Fanout Our SAT solver works on the circuit Propagating in the direction of fanins is easy Propagating in the direction of fanouts requires having fanout info available Using global fanout info (fanouts for all nodes) is not efficient This is because SAT solver propagates constraints to all fanouts, including those outside of the cone of influence of the target node(s) This is why we maintain local fanout info Only for the nodes in the window (excluding side nodes and their fanouts) Local fanout is kept in a dedicated manager and dynamically updated Boolean network (AIG) Target node whose value is computed by the SAT solver Useless fanouts Useful fanouts Current window Node looked at by the solver

Local Structural Support When SAT solver produces a counter-example, window is re-simulated In the process, even nodes whose values did not change are re-simulated Computation can be improved using structural support of the nodes This way re-simulation is applied to a fraction of the nodes, which greatly reduces runtime, without changing the quality Representing global structural support takes more time and memory This is why we keep local supports, only for the nodes in the window Local support is kept in a dedicated manager and dynamically updated Boolean network (AIG) Target node whose value is computed by simulation A fraction of the window is resimulated when support information is used The complete window is resimulated when support information is not used Primary inputs whose values have changed

Deeper Integration of Simulation and SAT Recall that previous work resorts to batching Collects and re-simulates N (for example, N=16) assignments at once Simulation does not take too much time (but still slow) SAT solver does not slow down too much (but still slow) In this work, we propose a better solution The idea is to perform eager re-simulation (no batching) of satisfying assignments while relying a deeper integration of simulation and SAT The runtime is not a problem because Circuit-based solver is fast (due to the use of local fanout) and generates incomplete assignments Simulator is fast (due to the use of local support) because it re-simulates only affected nodes in the window The cumulative runtime reduction of SAT sweeping is 2-5x

Experimental Results These are preliminary experiments, comparing two solvers CNF-based SAT solver MiniSAT Circuit-based solver CBS used in the proposed ecosystem The benchmarks considered are two large AIGs encountered in Sequential signal correspondence (command scorr in ABC) Computing structural choices (command dch in ABC)

Experimental Results

Conclusion Reviewed state-of-the-art in simulation and SAT Motivated the need for a deeper integration Showed how to achieve a deeper integration by developing a novel ecosystem for SAT sweeping based on simulation and SAT The proposed circuit-based SAT solver uses local fanout for efficient solving in the window, resulting in incomplete satisfying assignments The incomplete assignments are passed to the simulator, which re-simulates them eagerly (without batching), resulting in timely refinement of equivalences Developed a new AIG package to enable efficient windowing and managing local fanouts/supports in the window Experimental results show that the circuit-based solver is efficient Future work Finish integration and tuning of SAT and simulation Propagate changes to relevant ABC packages (cec, &cec, scorr, &scorr, pdr, …) Customize circuit-based solver for different netlists (AIG, XAIG, MIG, 4LUT, etc)

Abstract This paper focuses on problems where the interdependence of simulation and Boolean satisfiability (SAT) is critical. A modified AIG data-structure is proposed to optimize the speed of logic manipulation for large problems of this type. Experimental results confirm that the new implementation is faster, compared to the old one, in which runtime and scalability has been a known issue.